compiler-errors - “'附近” : syntax error

Question

我在VHDL中编写了以下代码:

library IEEE ;
use IEEE.STD_LOGIC_1164.all ;


entity encoder is 
port(
    x : in std_logic_vector (7 downto 0);
  en : in std_logic ;
  y : out std_logic_vector (2 downto 0));
end encoder;

architecture enc_arch of encoder is 
begin

  process(en,x) 
  begin 
    if (en ='0') then
      y<= "000";
    else 
      y<= "001" when (x = '00000010') else
          '010' when (x = '00000100') else 
          '011' when (x = '00001000') else 
          '100' when (x = '00010000') else 
          '101' when (x = '00100000') else 
          '110' when (x = '01000000') else 
          '111' when (x = '10000000') else
          '000' ;
    end if ;
  end process ;

end enc_arch;

错误是:

vhd(20): near "'": syntax error

vhd(30): VHDL Compiler exiting

谁能帮助我解决这些问题？

Answer 1

(x = '10000000')(以及所有类似的行)应将''更改为“”:(x = "10000000")
这是因为单引号用于std_logic，而双引号用于std_logic_vector。

也:
{library IEEE ;应该是:library IEEE ;
并且end enc_arch;}应该是end enc_arch;