compiler-errors - 类型转换不能有聚合操作数(modelsim中的错误)

Question

我是VHDL的新手。在modelsim6.5b中编译时出现以下错误

1. type conversion(to g) cannot have aggregate operand,
2. No feasible entries for infix operator "and",
3. Target type ieee.std_logic_1164.std_ulogic in variable assignment is different from - expression type std.stadard.integer

这些方面的任何帮助及其背后的原因都将有所帮助。

这是我写的包裹

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

package enc_pkg is

    constant n       : integer := 1;
    constant k       : integer := 2;
    constant m       : integer := 3;
    constant L_total : integer := 10;
    constant L_info  : integer := 10;

    type t_g is array (1 downto 1, 3 downto 1)of std_logic;
    signal g:t_g;
    type array3_10 is array (3 downto 1, 10 downto 0) of std_logic;
    type array2_10 is array (2 downto 1, 10 downto 0) of std_logic;

    procedure rsc_encoder(
        x          : in  std_logic_vector(1 to 10);
        terminated : in  std_logic;
        y          : out array2_10);


    procedure encode_bit(input     : in  std_logic;
                         state_in  : in  std_logic_vector(1 to 2);
                         output    : out std_logic_vector(1 to 2);
                         state_out : out std_logic_vector(1 to 2));


    procedure encoderm
        (infor_bit : in  std_logic_vector(1 to 8);
         en_output : out std_logic_vector(1 to 20));

end enc_pkg;

package body enc_pkg is

    procedure rsc_encoder(
        x          : in  std_logic_vector(1 to 10);
        terminated : in  std_logic;
        y          : out array2_10)is

        variable state      : std_logic_vector(1 to 2);
        variable d_k        : std_logic;
        variable a_k        : std_logic;
        variable output_bit : std_logic_vector(1 to 2);
        variable state_out  : std_logic_vector(1 to 2);
    begin
        for i in 1 to m loop
            state(i) := '0';
        end loop;
        for i in 1 to L_total loop
            if(terminated = '0' or (terminated = '1' and i <= L_info))
            then
                d_k := x(i);
            elsif(terminated = '1' and i > L_info)then
                d_k := (g(1, 2) and state(1)) xor (g(1, 3) and state(2));
            end if;
            a_k           := (g(1, 1) and d_k) xor (g(1, 2) and state(1)) xor (g(1, 3)) and state(2));
            encode_bit(a_k, state, output_bit, state_out);
            state         := state_out;
            output_bit(1) := d_k;
            y(1, i)       := output_bit(1);
            y(2, i)       := output_bit(2);
        end loop;
    end rsc_encoder;


    procedure encode_bit(input     : in  std_logic;
                         state_in  : in  std_logic_vector(1 to 2);
                         output    : out std_logic_vector(1 to 2);
                         state_out : out std_logic_vector(1 to 2))is

        variable temp : std_logic_vector(1 to 2);
    begin
        for i in 1 to n loop
            temp(i) := g(i, 1) and input;
            for j in 2 to k loop
                temp(i) := temp(i) xor (g(i, j) and state_in(j-1));
            end loop;
        end loop;
        output    := temp;
        state_out := input & state_in(m-1);
    end encode_bit;


    procedure encoderm
        (infor_bit : in  std_logic_vector(1 to 8);
         en_output : out std_logic_vector(1 to 20))is
--type array2_10 is array (2 downto 1, 10 downto 0) of integer;
--type  array3_10 is array (3 downto 1, 10 downto 0) of integer;
        variable interleaved : std_logic_vector(1 to 10);
        variable input       : std_logic_vector(1 to 10);
        variable puncture    : std_logic;
        variable output      : array3_10;
        variable y           : array2_10;
        variable en_temp     : std_logic_vector(1 to 10);

    begin
        input := "0000000000";
        for i in 1 to 8 loop
            input(i) := infor_bit(i);
        end loop;
        rsc_encoder(input, terminated 1, y);
        for i in 1 to 10 loop
            output(1, i) := y(1, i);
            output(2, i) := y(2, i);
        end loop;

        interleaved(1)  := output(1, 1);
        interleaved(2)  := output(1, 4);
        interleaved(3)  := output(1, 7);
        interleaved(4)  := output(1, 10);
        interleaved(5)  := output(1, 2);
        interleaved(6)  := output(1, 5);
        interleaved(7)  := output(1, 8);
        interleaved(8)  := output(1, 3);
        interleaved(9)  := output(1, 6);
        interleaved(10) := output(1, 9);

        rsc_encoder(interleaved, terminated 0, y);

        for i in 1 to 10 loop
            output(3, i) := y(2, i);
        end loop;

        if puncture = '1'then
            for i in 1 to 10 loop
                for j in 1 to 3 loop
                    en_output(3*(i-1)+j) := output(j, i);
                end loop;
            end loop;
        elsif puncture = '0' then
            for i in 1 to L_total loop
                en_temp(n*(i-1)+1) := output(1, i);
                if((i rem 2) = 1)then
                    en_temp(n*i) := output(2, i);
                else

                    en_temp(n*i) := output(3, i);
                end if;
            end loop;
        end if;
        en_output := en_temp;
    end encoderm;

end enc_pkg;

Answer 1

让我们看一小段代码:

type g is array (1 downto 1, 3 downto 1)of integer;

...

variable state      : std_logic_vector(1 to 2);

...

a_k           := (g(1, 1) and d_k) xor (g(1, 2) and state(1)) xor (g(1, 3)) and state(2));

两件事情:

种类
g是一种类型，而不是信号...

做这样的事情。首先，您在VHDL中定义一个新类型。然后，您创建(现在说C)这个新创建类型的“变量”。在这个(再说一遍C)“变量”上，您要做的事。

type t_g is array (1 downto 1, 3 downto 1)of integer;
signal g: t_g;

运算符(operator)
g(1,2)是整数， state(1)是std_logic。这两种类型都没有 and运算符。您是否需要以下内容:

if state(1) = '1' then
   ....
else
   ....
end if;