compiler-errors - 是什么原因导致此VHDL代码中的 “Data type not implemented for operator ' COMPARE'”？

Question

我正在尝试比较两个变量:

variable E1, E2 : unsigned(5 downto 0);

与:

if (E1 < E2) then
lt_val := '1';
end if;

但是当我尝试编译时会出现该错误。

我不知道我在做什么错。

编辑:这是完整的文件，我将unsigned改回std_logic_vector并使用了numeric_std库。

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity FPA is
    port (clk, st : in  std_logic;
          d1      : in  std_logic_vector(15 downto 0);
          d2      : in  std_logic_vector(15 downto 0);
          sum     : out std_logic_vector(15 downto 0);
          rdy     : out std_logic);

end FPA;

architecture behav of FPA is

    type state is (s0, s1, s2, s3, s4, s5, s6, s7);
    signal new_state : state;
    signal norm      : std_logic;
    signal lt, gt    : std_logic;

begin

    process is
        variable curr_state : state := s7;
    begin
        if clk = '1' then
            case curr_state is
                when s0 =>
                    if st = '1' then curr_state := s1;
                    end if;
                when s1 =>
                    curr_state := s2;
                when s2 =>
                    if gt = '1' then curr_state := s4;
                    end if;
                    if lt = '1' then curr_state := s3;
                    end if;
                    if not((lt = '1') or (gt = '1')) then
                        curr_state := s5;
                    end if;
                when s3 =>
                    curr_state := s1;
                when s4 =>
                    curr_state := s1;
                when s5 =>
                    if norm = '1' then
                        curr_state := s6;
                    else
                        curr_state := s7;
                    end if;
                when s6 =>
                    curr_state := s7;
                when s7 =>
                    if st = '0' then curr_state := s0;
                    end if;
            end case;
            new_state <= curr_state;
        end if;
        new_state <= curr_state;
        wait on clk;
    end process;

    process is
        variable E1                : std_logic_vector(5 downto 0);
        variable E2                : std_logic_vector(5 downto 0);
        variable sum_val           : std_logic_vector(15 downto 0);
        variable X, Y              : std_logic_vector(11 downto 0);
        variable SGR               : std_logic_vector(11 downto 0);
        variable rdy_val, norm_val : std_logic;
        variable gt_val, lt_val    : std_logic;
    begin

        -- defaults

        rdy_val := '0';
        case new_state is

            when s0 =>
                sum_val := "ZZZZZZZZZZZZZZZZ";
                E1      := d1(15 downto 10);
                X       := "01" & d1(9 downto 0);
                E2      := d2(15 downto 10);
                Y       := "01" & d2(9 downto 0);
            when s1 =>
                if (E1 < E2) then
                    lt_val := '1';
                end if;
                if (E1 > E2) then
                    gt_val := '1';
                end if;
                SGR := X + Y;
            when s2 =>
                if SGR(11) = '1' then
                    norm_val := '1';
                end if;
            when s3 =>
                X  := X ror 1;
                E1 := E1 + "000001";
            when s4 =>
                Y  := Y ror 1;
                E2 := E2 + "000001";
            when s5 =>
            when s6 =>
                SGR := SGR ror 1;
                E2  := E2 + "000001";
            when s7 =>
                sum_val := E2 & SGR(9 downto 0);
                rdy_val := '1';
        end case;

        rdy  <= rdy_val;
        lt   <= lt_val;
        gt   <= gt_val;
        sum  <= sum_val;
        norm <= norm_val;

        wait on new_state;
    end process;

end behav;

Answer 1

将E1和E2声明为unsigned是正确的选择，但还不够。

您需要将其他几个变量声明为unsigned，将输入从std_logic_vector动态转换为unsigned，然后动态地将变量sum_val转换回std_logic_vector，以分配输出sum。

修补以下行似乎可以(至少可以在ModelSim中编译):

    variable E1                : unsigned(5 downto 0);
    variable E2                : unsigned(5 downto 0);
    variable sum_val           : unsigned(15 downto 0);
    variable X, Y              : unsigned(11 downto 0);
    variable SGR               : unsigned(11 downto 0);
    -- ...
    E1      := unsigned(d1(15 downto 10));
    X       := unsigned("01" & d1(9 downto 0));
    E2      := unsigned(d2(15 downto 10));
    Y       := unsigned("01" & d2(9 downto 0));
    -- ...
    sum  <= std_logic_vector(sum_val);