compiler-errors - VHDL-分配默认值

Question

我有以下架构:

architecture datapath of DE2_TOP is

begin
  U1: entity work.lab1 port map ( --error on this line
    clock => clock_50,
    key => key,
    hex6 => hex6,
    hex5 => hex5,
    hex4 => hex4
  );

end datapath;

这种体系结构显然取决于lab1实体。这是我的lab1实体和架构:

entity lab1 is
    port(
        clock : in std_logic;
        key : in std_logic_vector(3 downto 0);
        hex4, hex5, hex6 : out std_logic_vector(6 downto 0);
        value_counter   : in unsigned(7 downto 0);
        register_counter : in unsigned(3 downto 0)
        );
end lab1;

architecture up_and_down of lab1 is
    signal hex5_value : unsigned(7 downto 0);
        begin
    process(clock)
        begin
            value_counter<="00000000"; --default values?
            register_counter<="0000";
            if rising_edge(clock) then
                if (key(3)='0' and key(2)='0' and key(1)='1' and key(0)='0') then
                    value_counter <= value_counter + "1";   
                elsif (key(3)='0' and key(2)='0' and key(1)='0' and key(0)='1') then  
                    value_counter <= value_counter - "1";   
                end if;
            end if;
            hex5_value <= (value_counter - (value_counter mod 10))/10;
    end process;

end architecture up_and_down;

我收到以下错误:指示行上的 Error (10346): VHDL error at DE2_TOP.vhd(280): formal port or parameter "value_counter" must have actual or default value。在我看来，我已经在我的lab1体系结构中设置了默认值。有人知道是什么问题吗？

Answer 1

那不是一个“默认值”，而是一个初始化它的赋值。它还将分配给非法的输入端口。同样，该实体在架构之前进行编译，因此(非法)分配尚不存在。

signal value_counter : unsigned(7 downto 0) := (others => 'X'); 

是声明中提供的默认值(或初始值)

port (
   value_counter   : in unsigned(7 downto 0) := (others => '1'); 

将是输入端口上的默认值，但我从未见过这样做。
我一直在连接端口图中的所有输入端口。如果这行得通，我会(对)印象深刻，但可能不足以对未连接的输入感到满意；以这种方式忽略错误似乎太容易了。