verilog - Verilog 中的低延迟 FWFT Fifo

Question

我有下面的代码，我尝试在verilog中实现低延迟第一个字失败fifo。

   reg [width-1:0]       mem [depth-1:0];

   always @ (posedge clk) begin
      if (wr_en) begin
         mem[wr_pointer[address_width-1:0]] <= #1 din;
      end
   end

   assign #1 dout = mem[rd_pointer[address_width-1:0]];

   always @ (posedge clk) begin
      if (reset) begin
         wr_pointer <= #1 0;
      end else if (wr_en) begin
         wr_pointer <= #1 wr_pointer + 1'b1;
      end
   end

   always @ (posedge clk) begin
      if (reset) begin
         rd_pointer <= #1 0;
      end else if (rd_en) begin
         rd_pointer <= #1 rd_pointer + 1'b1;
      end
   end

我综合它并收到以下消息:

INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_mem> will be implemented on LUTs 
either because you have described an asynchronous read or because of currently
unsupported block RAM features. If you have described an asynchronous read, 
making it synchronous would allow you to take advantage of available block RAM
resources, for optimized device usage and improved timings. Please refer to 
your documentation for coding guidelines.

有人可以向我解释一下这条消息吗？我不认为这需要异步读取。我只在时钟沿修改读指针。还有什么我错过的事情吗？

Answer 1

下面的行是您的异步​​读取:

assign #1 dout = mem[rd_pointer[address_width-1:0]];

将其更改为类似下面的代码以使其同步。

reg [width-1:0] dout;
always @ (posedge clk) begin
   if (reset) begin
      dout <= #1 0;
   end else if (rd_en) begin
      dout <= #1 mem[rd_pointer[address_width-1:0]]
   end
end

异步读取意味着内存中的所有字必须随时可用，因为内存地址可能随时更改(而不仅仅是在时钟沿)。

由于异步读取需要访问所有内存字，因此 FPGA 无法使用片上 RAM。片上 RAM 有一条读总线，只能访问存储器中的一个字，并在时钟沿发生变化。因此，用一堆 LUT 来构建内存。在这种情况下，您可以将内存视为由触发器的二维数组构建而成，现在它可以连接到所有单词。