gcc - 如何在没有任何循环或分支的情况下强制 CPU 按顺序执行程序？

Question

这可能吗？对于没有任何分支/循环的小代码。是否有任何 gcc 标志或像 SSE 那样用于 x86 和其他处理器系列的内部指令？我很好奇，因为现在所有可用的处理器都遵循乱序执行模型。

提前致谢

Answer 1

大多数现代乱序 CPU 本质上都是乱序的，无法在有序和乱序模式之间切换。

你可以尝试找一些有序的CPU，有一些:

• x86:Intel Atom(仅 45 nm 及更早版本；它们有两条并行管道，但按顺序执行所有指令)
• arm:Cortex-A8 和许多旧内核；

虽然在典型的乱序 CPU 中无法直接关闭指令重新排序，但您可以注入(inject)一些序列化(如 x86 世界中的 cpuid)在您的每条指令之间模拟按顺序执行。

英特尔手册 ( vol 3a ) 中有一部分是关于序列化指令的(从 http://objectmix.com/asm-x86-asm-370/69413-serializing-instructions.html 复制而来):

Volume 3A: System Programming Guide states

7.4 SERIALIZING INSTRUCTIONS

The Intel 64 and IA-32 architectures define several serializing instructions. These instructions force the processor to complete all modifications to flags, registers, and memory by previous instructions and to drain all buffered writes to memory before the next instruction is fetched and executed. For example, when a MOV to control register instruction is used to load a new value into control register CR0 to enable protected mode, the processor must perform a serializing operation before it enters protected mode. This serializing operation insures that all operations that were started while the processor was in real-address mode are completed before the switch to protected mode is made.

The concept of serializing instructions was introduced into the IA-32 architecture with the Pentium processor to support parallel instruction execution. Serializing instructions have no meaning for the Intel486 and earlier processors that do not implement parallel instruction execution.

It is important to note that executing of serializing instructions on P6 and more recent processor families constrain speculative execution because the results of speculatively executed instructions are discarded. The following instructions are serializing instructions:

o Privileged serializing instructions - MOV (to control register, with the exception of MOV CR8), MOV (to debug register), WRMSR, INVD, INVLPG, WBINVD, LGDT, LLDT, LIDT, and LTR.

o Non-privileged serializing instructions - CPUID, IRET, and RSM.

When the processor serializes instruction execution, it ensures that all pending memory transactions are completed (including writes stored in its store buffer) before it executes the next instruction. Nothing can pass a serializing instruction and a serializing instruction cannot pass any other instruction (read, write, instruction fetch, or I/O). For example, CPUID can be executed at any privilege level to serialize instruction execution with no effect on program flow, except that the EAX, EBX, ECX, and EDX registers are modified.