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vhdl - 进程语法错误

转载 作者:行者123 更新时间:2023-12-02 05:17:52 25 4
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我正在尝试模拟我的小程序,但我不断收到错误消息,但我无法找出原因。

错误消息是:

line 131 error near process

line 132 error near behavioral ; expected type void

行:

 130    end if;
131 end process;
132 end Behavioral;

我已经尝试解决这些问题几个小时了,但我仍然没有任何线索。

完整代码:

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kuutonen is
Port ( A1 : in STD_LOGIC;
B1 : in STD_LOGIC;
clk : in STD_LOGIC;
A : out STD_LOGIC;
B : out STD_LOGIC;
C : out STD_LOGIC;
D : out STD_LOGIC;
E : out STD_LOGIC;
F : out STD_LOGIC;
G : out STD_LOGIC);
end kuutonen;

architecture Behavioral of kuutonen is
signal tmp : std_logic_vector (2 downto 0);
begin

process (clk)
begin
if(tmp = "110")then
tmp <= "000";
end if;

if (A1 = '0' and B1 = '0') then
if (tmp ="000") then
A <= '1';
B <= '0';
C <= '0';
D <= '0';
E <= '0';
F <= '0';
G <= '0';
tmp <= tmp + 1;
end if;

if (tmp ="001")then
B <= '1';
A <= '0';
C <= '0';
D <= '0';
E <= '0';
F <= '0';
G <= '0';
tmp <= tmp + 1;
end if;

if (tmp ="010")then
C <= '1';
B <= '0';
A <= '0';
D <= '0';
E <= '0';
F <= '0';
G <= '0';
tmp <= tmp + 1;
end if;

if (tmp ="011")then
D <= '1';
B <= '0';
C <= '0';
A <= '0';
E <= '0';
F <= '0';
G <= '0';
E <= '1';

if (tmp ="100")then
E <= '1';
B <= '0';
C <= '0';
D <= '0';
A <= '0';
F <= '0';
G <= '0';
tmp <= tmp+1;
end if;

if (tmp ="101")then
F <= '1';
B <= '0';
C <= '0';
D <= '0';
E <= '0';
A <= '0';
G <= '0';
tmp <= tmp+1;
end if;

if (tmp ="110")then
G <= '1';
B <= '0';
C <= '0';
D <= '0';
E <= '0';
F <= '0';
A <= '0';
end if;

end if;
end process;
end Behavioral;

最佳答案

仅从检查来看,我认为这可能是由于缺少“end if;” tmp=001 和 tmp=100 的情况之间。

关于vhdl - 进程语法错误,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/8675825/

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