VHDL:两个数字相加时发生边界检查错误

Question

为什么这个 VHDL 代码会导致边界检查失败？我的结果信号比添加的最宽数字宽 1 位...因此它不应该溢出...我错过了什么吗？

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench is
end entity;

architecture sim of testbench is
    constant dw       :natural                 := 8;
    signal   arg1     :unsigned(dw-1 downto 0) := to_unsigned(4, dw);       
    signal   result   :unsigned(dw+0 downto 0);
begin
    result <= arg1 + '1';
end architecture;

C:> ghdl -a --std=08 --ieee=synopsys --work=work testbench.vhd

C:> ghdl --elab-run --std=08 --ieee=synopsys testbench --ieee-asserts=disable

ghdl.exe:error: bound check failure at testbench.vhd:13 from: process work.testbench(sim).P0 at testbench.vhd:13

ghdl.exe:error: simulation failed

Answer 1

加法的向量操作数应与赋值的目标具有相同的长度。如果需要的话可以扩展:

result <= ('0' & arg1) + '1';