syntax - => 和 <= 之间的 VHDL 区别

Question

我总是忘记，很难在教科书或互联网上寻找答案。

Answer 1

嗯，<=是作业。

signal <= A or B;

=> case 语句使用的语法如下:(盗自http://www.cs.umbc.edu/portal/help/VHDL/sequential.html)

case  my_val  is
  when 1 =>  -- This is kind of like how the : operator is used for switch in many languages
    a:=b;
  when 3 =>
    c:=d;
    do_it;
  when others =>
    null; -- do nothing
end case;

end case;

=>也可以用于数组赋值

myVector <= (1=>'1', OTHERS=>'0');  -- assigns ('0','1','0','0') to "myVector"

来源:http://www.eda.org/comp.lang.vhdl/html3/gloss_example.html