vhdl - 为什么JK触发器的输出在仿真中是红色的？

Question

我正在发布 VHDL 语言的 JK 触发器代码。根据JK触发器电路，代码是正确的。但我得到的输出是红线。谁能告诉我只有 JK 触发器有什么问题。

• 程序:JK 触发器

------------=======N和三输入门=====----------------

library ieee;
 use ieee.std_logic_1164.all;
 entity nand_gate3 is port(
       A, B, C : in std_logic;
             F : out std_logic);
 end nand_gate3 ;


 architecture nandfunc3 of nand_gate3 is
  signal x : std_logic ;
 begin
      x <= A nand B ;
      F <= x nand C ;
end nandfunc3;

------====== END NANd GATE  with three inout ======--------

----=========NANd Gate with Two inputs==========------------
 library ieee;
use ieee.std_logic_1164.all;
 entity nand_gate2 is port(
          A, B : in std_logic;
             F : out std_logic );
end nand_gate2;

architecture nandFunc2 of nand_gate2 is
begin
      F <= A nand B ;
end nandFunc2;
------====== END NANd GATE  with three inout ======-
library ieee;
 use ieee.std_logic_1164.all;
 ENTITY  JK_flipflop IS PORT ( 
                     clk , J, K : IN  std_logic; 
                     Q , Q_bar  : OUT std_logic );
 END JK_flipflop ;  

 architecture JK_structure OF JK_flipflop  IS 
 ----===Compnents 
    COMPONENT nand_gate3 IS PORT (
                       A, B ,C  : IN std_logic ; 
                       F        : OUt std_logic );
    End Component ; 

    COMPONENT nand_gate2 IS PORT (
                       A, B   : IN std_logic ; 
                       F        : OUt std_logic );
    End Component ; 

    Signal X, Y , Qback ,Qbar_back: std_logic ; 
----== Structure
  Begin 

   U1: nand_gate3 PORT MAP ( J, clk, Qbar_back, X ); 
   U2: nand_gate3 PORT MAP ( K, clk, Qback    ,Y );
  U3: nand_gate2 PORT MAP ( X, Qbar_back  ,Qback); 
  U4: nand_gate2 PORT MAP ( Y, Qback  ,Qbar_back); 

   Q <= Qback;
    Q_bar <= Qbar_back;

END JK_structure ; 

--------------------JK触发器的测试台----===

 library ieee;
 use ieee.std_logic_1164.all; 

 entity jk_flipflop_tb is 
 end jk_flipflop_tb ;

   architecture tb of jk_flipflop_tb is
   ---====Jk_flipflop 
    component   JK_flipflop is  port(
                 clk,J , K  : in std_logic;
                 Q, Q_bar   : out std_logic);
   end component;
---===signals
   signal clk,J ,K , Q, Q_bar : std_logic;

   begin
    mapping:   JK_flipflop port map(clk, J, K, Q, Q_bar);

-------=========Process for Clcok ===========---------------
    process

 begin
    clk <= '1';
    wait for 5 ns;
    clk <= '0';
    wait for 5 ns;
   end process;
 --------===========Process for j,k inputs values=======--------------
 process

 begin
 -------===TEST 1
  J <= '0';
  K <= '1';
    wait for 20 ns;
  -------====TEST 2
   J <= '1';
   K <= '1';
   wait for 20 ns;
 -------====TEST 3
  J <= '1';
  K <= '0';
   wait for 20 ns;
 -------====TEST 4
   J <= '0';
   K <= '0';
  wait for 20 ns;

  end process;
end tb;
--------------------------------------------
 configuration cfg_tb of jk_flipflop_tb is
  for tb
  end for;
end cfg_tb;

----------======------

Answer 1

JK触发器必须有一个复位端口来初始化输出，否则因为输出(Q，Qbar)是自己设置的(反馈)，如果他们不有任何初始值，它们总是未定义的。然后您应该在您的设计中添加一个复位端口。

您可以使用以下代码来获得正确的结果:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JK_FF is
    port( 
        Reset  : in  std_logic;
        Clock  : in  std_logic;
        J,K    : in  std_logic;
        Q,Qbar : out std_logic
    );
end JK_FF;

architecture Behavioral of JK_FF is
    signal temp : std_logic;
begin
    process (Clock) 
    begin
        if rising_edge(Clock) then                 
            if Reset='1' then   
                temp <= '0';
            else
                if (J='0' and K='0') then
                    temp <= temp;
                elsif (J='0' and K='1') then
                    temp <= '0';
                elsif (J='1' and K='0') then
                    temp <= '1';
                elsif (J='1' and K='1') then
                    temp <= not (temp);
                end if;
            end if;
        end if;
    end process;

    Q <= temp;
    Qbar <= not temp;

end Behavioral;