verilog : Variable index is not supported in signal

Question

我收到一条错误消息，提示“信号不支持索引”。据我所见，错误出现在非阻塞分配的左侧。为什么下面的代码会出错，是否有解决方法？

...
parameter width = 32;
parameter size = 3;

input clk, reset;
input [width*size-1:0] A;
input [width*size-1:0] B;
output [width*size-1:0] result;

reg signed [width*size-1:0] partials;
reg signed [width-1:0] temp;
reg signed [width-1:0] currenta;
reg signed [width-1:0] currentb;
wire signed [width-1:0] temp1wire;
...
integer k = 0;
always @ (posedge clk)
begin
    currenta[width-1:0] <= A[width*k +: width];
    k = k+1
    currentb[width-1:0] <= B[width*k +: width];
    partials[width*k +: width] <= temp1wire;
end
Add Add1(clk, temp1wire, currenta, currentb);
...

此代码是执行向量加法并将结果保存在 partials[width*k +: width] 的顺序 block 的一部分。

Answer 1

我找到了 this在 Xilinx 论坛上:

"XST works fine with the indexed part-select operator "+:" if it is on the right-hand side (RHS) of the assignment. It also works fine when it is on the left-hand side (LHS) AND the starting index is a constant. Your case uses a variable as the starting index on the LHS and that what XST doesn't like although it's legal."