verilog - 输入和输出信号未显示在 Modelsim10.1c 的对象窗口中

Question

我是在 modelsim 中使用 verilog 设计电路的初学者。我使用示例代码和教程来了解 modelsim 的工作原理。代码和测试平台的编译没有任何问题，甚至测试平台的模拟也没有任何错误，但输入和输出信号未显示在对象窗口中，并且它们不在实例菜单下。请为我描述如何找到它们并模拟波形。这是我的代码和测试台。D触发器的定义

// module D_FF with synchronous reset
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
// Lots of new constructs. Ignore the functionality of the
// constructs.
// Concentrate on how the design block is built in a top-down fashion.
always @(negedge clk or posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;
endmodule

D中T触发器的定义

module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q);
endmodule

计数器代码:

module rcc4(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
endmodule

测试台代码:

module stimulus();
reg clk;
reg reset;
wire[3:0] q;
// instantiate the design block
rcc4 r1(q, clk, reset);
// Control the clk signal that drives the design block. Cycle time = 10
initial
clk = 1'b0; //set clk to 0
always
#5 clk = ~clk; //toggle clk every 5 time units
// Control the reset signal that drives the design block
// reset is asserted from 0 to 20 and from 200 to 220.
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish; //terminate the simulation
end
// Monitor the outputs
initial
$monitor($time, " Output q = %d", q);
endmodule

我在 Windows 10 上使用 modelsim 10.1c。 The following picture is from my project and it shows my object and instance window.

Answer 1

开关 -voptargs=+acc 将解决您的问题。

vsim -voptargs=+acc modulename