vhdl - VHDL 中是否定义了整数溢出？

Question

我想知道VHDL中是否定义了整数溢出。我在 2002 年规范中找不到任何内容。

作为示例(注意，这可能无法编译，它只是一个通用示例...):

entity foo is port (
    clk : std_logic
);
end entity;

architecture rtl of foo is
    signal x : integer range 0 to 2 := 0;
begin
    process (clk)
    begin
        if rising_edge(clk) then
            x <= x + 1;
        end if;
    end process;
end architecture;

很明显，x将从0到1，然后到2。是否定义了下一个增量会发生什么？这是未定义的行为吗？

Answer 1

对于 ghdl 中 foo 的 rtl 测试台:

ghdl -r foo_tb --wave=foo_tb.ghw
./foo_tb:error: bound check failure at foo_tb.vhdl:15
./foo_tb:error: simulation failed

我向 Bill 的 foo 实体和架构添加了一个上下文子句:

library ieee;
use ieee.std_logic_1164.all;

entity foo is port (

第 15 行是对 x 的信号分配:

            x <= x + 1;

这是一个模拟错误(在运行时发生)。

来自 IEEE 1076-1993:

7.2.4 添加运算符

The adding operators + and - are predefined for any numeric type and have their conventional mathematical meaning.

这意味着“+”运算符的结果可以超出 x 的子类型约束。请注意，声明为“+”提供重载的函数不允许指定结果子类型。 (返回值可以是声明有子类型指示的对象，可以定义值范围或数组长度)。

和12.6.2信号值的传播

In order to update a signal during a given simulation cycle, the kernel process first determines the driving and effective values of that signal. The kernel process then updates the variable containing the current value of the signal with the newly determined effective value, as follows:

a) If S is a signal of some type that is not an array type, the effective value of S is used to update the current value of S. A check is made that the effective value of S belongs to the subtype of S. An error occurs if this subtype check fails. Finally, the effective value of S is assigned to the variable representing the current value of the signal.

如果加法的结果与目标 x 的子类型约束不匹配，则会生成错误。该子类型约束由对象 x 声明提供，该声明提供整数(范围)的子类型指示。

运行时错误导致模拟终止以实现符合 LRM 的实现。

如果没有标准化的错误报告格式，ghdl 不会提供当前的模拟时间。通过检查生成的波形可以发现:

波形在 20 ns 后完全更新。下一个预定事件:

library ieee;
use ieee.std_logic_1164.all;

entity foo_tb is
end entity;

architecture foo of foo_tb is
    signal clk: std_logic := '0';
begin
DUT:
    entity work.foo
        port map (
            clk => clk
        );
        
CLOCK:
    process
    begin
        wait for 5 ns;
        clk <= not clk;
        if now > 30 ns then
            wait;
        end if;
    end process;
    
end architecture;

应该是 25 ns 处的 clk 上升沿。

这告诉我们受约束的整数如何产生溢出错误。

没有子类型约束的整数怎么样:

architecture fum of foo is
    signal x : integer := INTEGER'HIGH - 2;
begin
    process (clk)
    begin
        if rising_edge(clk) then
            x <= x + 1;
        end if;
    end process;
end architecture;

我们将 x 定义为不受约束的整数，将其设置为我们期望 x 溢出的默认值。

包标准显式声明 INTEGER“+”:

--  function "+"      (anonymous, anonymous: INTEGER) return INTEGER;

如果我们看到“+”具有普通的数学含义，则预期结果超出了 INTEGER 的范围。

但是，从包标准中的实现相关声明来看:

type integer is range -2147483648 to 2147483647;

和模拟:

我们看到 x 的值环绕。

“+”运算符结果的赋值不违反任何约束:

3 种类型:

The set of possible values for an object of a given type can be subjected to a condition that is called a constraint (the case where the constraint imposes no restriction is also included); a value is said to satisfy a constraint if it satisfies the corresponding condition. A subtype is a type together with a constraint. A value is said to belong to a subtype of a given type if it belongs to the type and satisfies the constraint; the given type is called the base type of the subtype. A type is a subtype of itself; such a subtype is said to be unconstrained (it corresponds to a condition that imposes no restriction). The base type of a type is the type itself.

在我们的第二个架构中，没有约束，但没有可能的值超出 INTEGER 类型的声明范围。相反，该值会滚动。

VHDL 的语义已被构造为不需要在此处进行检测，这与表示二进制位(硬件)的元素的一维数组上的数学运算相匹配。