Verilog HDL 语法错误

Question

大家，只是一个关于如何修复以下 Verilog 代码的简单问题，我不断收到错误。有什么建议吗？

module bcd_to_seven_seg( B, S);

input wire [3:0]B;
output wire [6:0]S;

reg [6:0] rS;
assign S = rS;

always @(B)
begin
  case({B})
  4'b0000: rS= 7b'1000000;
  4'b0001: rS= 7b'1111001;
  4'b0010: rS= 7b'0100100;
  4'b0011: rS= 7b'0110000;
  4'b0100: rS= 7b'0011001;
  4'b0101: rS= 7b'0010010;
  4'b0110: rS= 7b'0000010;
  4'b0111: rS= 7b'1111000;
  4'b1000: rS= 7b'0000000;
  4'b1001: rS= 7b'0010000;
  endcase

end

endmodule

这是错误

Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(32) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(33) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(34) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(35) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(36) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(37) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(38) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(39) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(40) near text "b";  expecting ";"  
Error (10170): Verilog HDL syntax error at bcd_to_seven_seg.v(41) near text "b";  expecting ";"  
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 10 errors, 0 warnings  
  Error: Peak virtual memory: 556 megabytes  
  Error: Processing ended: Sun Nov 12 11:24:28 2017  
  Error: Elapsed time: 00:00:01  
  Error: Total CPU time (on all processors): 00:00:01

Answer 1

7'b0010001

7' 表示七位数字

b 表示您正在使用二进制

0010001是您的号码

我们都犯过同样的错误