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vhdl - VHDL 中的捆绑语句

转载 作者:行者123 更新时间:2023-12-01 13:09:17 27 4
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如何组合/捆绑语句以供进一步使用和更好地处理?例如,像这样的一些赋值会在以后的例程调用中多次使用。

ADDR_PC     <= "0000000000";
ADDR_OP_A <= "00000";
ADDR_OP_B <= "00000";
OP_CODE <= OP_NOP;
OP_IMMED <= IMMED_NULL;
WE_SREG <= "00000"; -- S V N C Z

变成这样。

NOP = {ADDR_PC <= "00000000", ADDR_OP_A <= "00000", ...}

我不知道是否有任何可能在 VHDL 中做到这一点。任何提示都会有所帮助。

最佳答案

记录和/或聚合:

library ieee;
use ieee.std_logic_1164.all;

entity op_decoded is
end entity;

architecture foo of op_decoded is
-- These declarations probably want to be in a package
constant IMMED_NULL: std_logic_vector (8 downto 0) := (others => '0');
constant OP_NOP: std_logic_vector (5 downto 0) := (others => '0');

type decode_op is
record
PC: std_logic_vector (7 downto 0);
OP_A: std_logic_vector (4 downto 0);
OP_B: std_logic_vector (4 downto 0);
OP_CODE: std_logic_vector (5 downto 0);
OP_IMMED: std_logic_vector (8 downto 0);
WE_SREG: std_logic_vector (4 downto 0); -- S V N C Z
end record;

constant NOP: decode_op := (
PC => "00000000",
OP_A => "00000",
OP_B => "00000",
OP_CODE => OP_NOP,
OP_IMMED => IMMED_NULL,
WE_SREG => "00000"
);
-- actual signals
signal ADDR_PC: std_logic_vector (7 downto 0);
signal ADDR_OP_A: std_logic_vector (4 downto 0);
signal ADDR_OP_B: std_logic_vector (4 downto 0);
signal OP_CODE: std_logic_vector (5 downto 0);
signal OP_IMMED: std_logic_vector (8 downto 0);
signal WE_SREG: std_logic_vector (4 downto 0);

signal pipe1: decode_op;
signal pipe_disc: decode_op;

begin
(ADDR_PC, ADDR_OP_A, ADDR_OP_B, OP_CODE, OP_IMMED, WE_SREG) <= NOP;

pipe1 <= NOP;

pipe_disc <= (pipe1.PC, pipe1.OP_A, pipe1.OP_B, pipe1.OP_CODE,
pipe1.OP_IMMED, pipe1.WE_SREG);

end architecture;

这会分析、阐述和模拟(表明它在句法和语义上都是正确的)。

还有一个带有聚合右侧的聚合目标(提供的类型):

     (ADDR_PC, ADDR_OP_A, ADDR_OP_B, OP_CODE, OP_IMMED, WE_SREG) <= 
decode_op'(pipe1.PC, pipe1.OP_A, pipe1.OP_B, pipe1.OP_CODE,
pipe1.OP_IMMED, pipe1.WE_SREG);

关于vhdl - VHDL 中的捆绑语句,我们在Stack Overflow上找到一个类似的问题: https://stackoverflow.com/questions/32387473/

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