vhdl - 运行后重置输出

Question

我正在一个小项目中学习VHDL。目前，我正在开发BCD转换器(将二进制文件转换为其BCD编号)。

但是我在实施测试平台时陷入困境。应用模式后，它不会重置输出。

我的实体的VHDL代码:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_mod is
        port (
                entry: in std_logic_vector(16 downto 0);
                outp: out std_logic_vector(20 downto 0)
        );
end bcd_mod;

architecture calculate of bcd_mod is

begin
        process(entry)
                variable outp_cp : std_logic_vector(20 downto 0) := (others => '0');
                variable place : integer := 1;
                variable digit : integer := 0;
                variable number : integer := 0;

                begin

                        for i in 16 downto 0 loop
                                case entry(i) is
                                        when '0' => null;
                                        when '1' => number := number + (2**i);
                                        when others => null;
                                end case;
                        end loop;

                        if number > 99999 then
                                outp_cp(20) := '1';
                        else
                                while (number > 0) loop
                                        digit := number mod 10;

                                        if place = 1 then
                                                outp_cp(3 downto 0) := std_logic_vector(to_unsigned(digit, 4));
                                        elsif place = 2 then
                                                outp_cp(7 downto 4) := std_logic_vector(to_unsigned(digit, 4));
                                        elsif place = 3 then
                                                outp_cp(11 downto 8) := std_logic_vector(to_unsigned(digit, 4));
                                        elsif place = 4 then
                                                outp_cp(15 downto 12) := std_logic_vector(to_unsigned(digit, 4));
                                        else
                                                outp_cp(19 downto 16) := std_logic_vector(to_unsigned(digit, 4));
                                        end if;

                                        number := number - digit;
                                        number := number / 10;
                                        place := place + 1;
                                end loop;
                        end if;

                        outp <= outp_cp;
                        outp_cp := (others => '0');

        end process;

end calculate;

我的代码测试台:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_mod_testbench is
end bcd_mod_testbench;

architecture calculate of bcd_mod_testbench is
        component bmt
                port(entry : in std_logic_vector(16 downto 0); outp : out std_logic_vector(20 downto 0));
        end component;

        for bmt_0: bmt use entity work.bcd_mod;
                signal entry : std_logic_vector(16 downto 0);
                signal outp : std_logic_vector(20 downto 0);
                begin

        bmt_0: bmt port map (entry => entry, outp => outp);

        process
                type pattern_type is record
                        entry : std_logic_vector(16 downto 0);
                        outp : std_logic_vector(20 downto 0);
                end record;

                type pattern_array is array (natural range <>) of pattern_type;
                constant patterns : pattern_array :=
                (("00000110111101101", "000000011010101100101"),
                 ("00000000000000011", "000000000000000000011"),
                 ("00000000000011011", "000000000000000100111"));
                begin

                for i in patterns'range loop

                        entry <= patterns(i).entry;

                        wait for 1 ns;

                        assert outp = patterns(i).outp
                        report "Wrong BCD number." severity error;
                end loop;

                assert false report "End of test." severity note;
                wait;
        end process;
end calculate;

这是GTKWave中的输出。您可以在此处看到，在运行具有大数字的代码之后，以下数字从前一个数字结束处开始。


(可点击)

希望获得解决该问题的任何技巧。

Answer 1

在VHDL中，variable保留了两次重新输入之间的值。因此，当您输入数字X"000003"的过程时，所有变量仍具有在X"003565"处理结束时添加的值。

快速测试表明，在过程开始时将place设置为1可以解决此问题:

process(entry)
    variable outp_cp : std_logic_vector(20 downto 0) := (others => '0');
    variable place : integer := 1;
    variable digit : integer := 0;
    variable number : integer := 0;
begin
    place := 1;

    ...