system-verilog - 在 ANSI 样式的模块端口列表中使用参数化聚合数据类型

Question

以下代码

module test #(A = 1, B = 2) (output t_my sig);
   typedef struct {
      logic [A-1:0] fA;
      logic [B-1:0] fB;
   } t_my;
   initial $display("hello\n");
endmodule

返回 VCS 错误

Error-[SV-UIOT] Undefined interface or type
test.vs, 1
t_my, "sig"
  The definition for the forward-referenced interface 't_my' is missing or 
  't_my' is the name of an undefined user type.
  Check to see if the interface definition file/work library is missing or the
  definition of the user type is missing.

如果我改为

typedef struct {
   logic [A-1:0] fA;
   logic [B-1:0] fB;
}t_my;

module test #(A = 1, B = 2) (output t_my sig);
   initial $display("hello\n");
endmodule

然后我得到

Error-[IND] Identifier not declared
test.vs, 2
  Identifier 'A' has not been declared yet. If this error is not expected, 
  please check if you have set `default_nettype to none.


Error-[IND] Identifier not declared
test.vs, 3
  Identifier 'B' has not been declared yet. If this error is not expected, 
  please check if you have set `default_nettype to none.

有没有办法使用 ANSI 样式的模块端口列表来做我想做的事情？请注意，我可以在没有 ANSI 样式端口列表的情况下完成此操作，如下所示:

module test #(A = 1, B = 2) (sig); 
   typedef struct packed { 
       logic [A-1:0] fA; 
       logic [B-1:0] fB; } t_my; 

       output t_my sig; 
       initial $display("hello\n"); 
endmodule

module top; 
  logic topsig [2:0]; 
  test test1 (.sig ({>>{topsig}}) );
endmodule

Answer 1

当您在端口列表中有用户定义的聚合类型时，您需要将该类型放在兼容的位置以进行连接，即模块 测试 ，以及它上面的模块将与该端口建立连接。有两种方法可以做到这一点:

使用 从更高级别向下传递数据类型类型 范围。

module test#(type T) (input T sig);
   parameter A = $bits(sig.fA);
   parameter B = $bits(sig.fB);

   initial #1 $display(A,, B);
endmodule
module top;
   typedef struct {
      logic [3:0] fA;
      logic [4:0] fB;
   } my_t;

   my_t s;

   test #(my_t) t2(s);

endmodule 

显示

#           3           4

或者您可以将类型放在一个通用包中。但是，要使结构参数化，您需要将类型包装在一个类中。请参阅 1800-2012 LRM 的第 6.25 节(这应该是可合成的)

package p;
class T#(int A,B);
   typedef struct {
      logic [A-1:0] fA;
      logic [B-1:0] fB;
   } my_t;
endclass
endpackage : p

module test#(int A=1, B=2) (input p::T#(A,B)::my_t sig);
   initial #1 $displayb(sig.fA,, sig.fB);
endmodule

module top;
   import p::T;

   T#(2,3)::my_t s = '{'1, '1}; 
   test #(2,3) t(s);

endmodule