VHDL 边缘检测

Question

我想检测串行数据信号 (din) 上的边缘。我在 VHDL 中编写了以下代码，该代码运行成功，但检测到的边沿有一个时钟周期延迟，即在每个边沿有一个 clk_50mhz 周期延迟生成更改输出。任何人都可以帮我立即检测边缘。谢谢你。

 process (clk_50mhz)
 begin
        if clk_50mhz'event and clk_50mhz = '1' then
            if (rst = '0') then
                shift_reg <= (others => '0');
            else
                shift_reg(1) <= shift_reg(0);
                shift_reg(0) <= din;    
                        end if;      
        end if;
 end process;

    process (clk_50mhz)
    begin
        if clk_50mhz'event and clk_50mhz = '1' then
            if rst = '0' then
                change <= '0' ;
            elsif(clk_enable_2mhz = '1') then
                change <= shift_reg(0) xor shift_reg(1);                    
            end if ;
        end if ;
    end process ;

当我将代码更改为以下时，我能够检测到边缘

 process (clk_50mhz)
begin
    if clk_50mhz'event and clk_50mhz = '1' then
        if (RST = '0') then
            shift_reg <= (others=>'0');
        else
            shift_reg(1) <= shift_reg(0);
            shift_reg(0) <= din;    
  end if;     
    end if;
end process;

change <= shift_reg(1) xor din; 

Answer 1

干得好

library ieee;
use ieee.std_logic_1164.all;

entity double_edge_detector is
    port ( 
        clk_50mhz   : in std_logic;
        rst         : in std_logic;
        din         : in std_logic;
        change      : out std_logic
    );
end double_edge_detector;

architecture bhv of double_edge_detector is

signal din_delayed1 :std_logic;

begin
    process(clk_50mhz)
    begin
        if rising_edge(clk_50mhz) then
            if rst = '1' then
                din_delayed1 <= '0';
            else
                din_delayed1 <= din;
            end if;
        end if;

    end process;

    change <= (din_delayed1 xor din); --rising or falling edge (0 -> 1 xor 1 -> 0)


end bhv;