debugging - 如何使用 gdb 转储 ARM 协处理器寄存器？

Question

有没有办法从 gdb 转储 ARM(特别是 CP15 sctlr)的协处理器寄存器？我正在使用 code-sourcery (arm-none-linux-gnueabi-) 中的工具链并调试在 QEMU 上运行的 linux。

一种方法是在 mcr/mrc 指令之前/之后转储使用过的 GPR。还有其他方法吗？

Answer 1

据我所知，GDB/ARM 将无法显示此信息......但调试 qemu可能会帮助您(假设您可以使用其调试信息编译/调试 qemu):

将 GDB(i686 确定，但不是 ARM)附加到您的 qemu流程

看看这个文件:qemu/target-arm/cpu.h

检查类似 env->cp15 的内容或 gdbserver_state->g_cpu->cp15 * :

struct {
uint32_t c0_cachetype;
uint32_t c0_ccsid[16]; /* Cache size.  */
uint32_t c0_clid; /* Cache level.  */
uint32_t c0_cssel; /* Cache size selection.  */
uint32_t c0_c1[8]; /* Feature registers.  */
uint32_t c0_c2[8]; /* Instruction set registers.  */
uint32_t c1_sys; /* System control register.  */
uint32_t c1_coproc; /* Coprocessor access register.  */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
uint32_t c2_base0; /* MMU translation table base 0.  */
uint32_t c2_base1; /* MMU translation table base 1.  */
uint32_t c2_control; /* MMU translation table base control.  */
uint32_t c2_mask; /* MMU translation table base selection mask.  */
uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
uint32_t c2_data; /* MPU data cachable bits.  */
uint32_t c2_insn; /* MPU instruction cachable bits.  */
uint32_t c3; /* MMU domain access control register
                MPU write buffer control.  */
uint32_t c5_insn; /* Fault status registers.  */
uint32_t c5_data;
uint32_t c6_region[8]; /* MPU base/size registers.  */
uint32_t c6_insn; /* Fault address registers.  */
uint32_t c6_data;
uint32_t c9_insn; /* Cache lockdown registers.  */
uint32_t c9_data;
uint32_t c13_fcse; /* FCSE PID.  */
uint32_t c13_context; /* Context ID.  */
uint32_t c13_tls1; /* User RW Thread register.  */
uint32_t c13_tls2; /* User RO Thread register.  */
uint32_t c13_tls3; /* Privileged Thread register.  */
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
uint32_t c15_ticonfig; /* TI925T configuration byte.  */
uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
uint32_t c15_threadid; /* TI debugger thread-ID.  */
} cp15;

*我不确定确切的位置，只是基于 qemu/gdbstub.c 的一些猜测，但我无法实际测试它。