c++ - 多线程光线追踪器的噪声

Question

这是我的第一个多线程实现，所以它可能是初学者的错误。线程处理每第二行像素的渲染(因此所有渲染都在每个线程内处理)。如果线程分别渲染屏幕的上部和下部，问题仍然存在。

两个线程都读取相同的变量，这会导致任何问题吗？据我所知，只有写作会导致并发问题......

调用相同的函数会导致并发问题吗？再一次，据我所知，这应该不是问题......

唯一一次两个线程写入同一个变量是在保存计算出的像素颜色时。这存储在一个数组中，但它们从不写入该数组中的相同索引。这会导致问题吗？

Multi-threaded rendered image(防止垃圾邮件阻止我直接发布图片..)

附言。我在这两种情况下使用完全相同的实现，唯一的区别是为渲染创建的单个线程与两个线程。

Answer 1

Both threads read from the same variables, can this cause any problems? From what I've understood only writing can cause concurrency problems...

这应该没问题。显然，只要数据在两个线程开始读取之前初始化并在两个线程完成后销毁即可。

Can calling the same functions cause any concurrency problems? And again, from what I've understood this shouldn't be a problem...

是也不是。没有代码太难说了。该功能有什么作用？它是否依赖于共享状态(例如 static 变量、全局变量、单例...)？如果是，那么这绝对是个问题。如果从来没有任何共享状态，那么你没问题。

The only time both threads write to the same variable is when saving the calculated pixel color. This is stored in an array, but they never write to the same indices in that array. Can this cause a problem?

也许有时候。什么的数组？如果 sizeof(element) == sizeof(void*) 可能是安全的，但 C++ 标准在多线程上是静音的，因此它不会强制您的编译器强制您的硬件使其安全。您的平台可能会在这里咬住您(例如，64 位机器和一个写入 32 位的线程可能会覆盖相邻的 32 位值)，但这并不是一种罕见的模式。通常你最好使用同步来确保。

您可以通过多种方式解决此问题:

• 每个线程构建自己的数据，然后在它们完成时聚合。
• 您可以使用 mutex 来保护共享数据.

我的回答缺乏 promise 是多线程编程困难的原因:P

例如，来自 Intel® 64 and IA-32 Architectures Software Developer's Manuals ，描述了不同的平台如何保证不同级别的原子性:

7.1.1 Guaranteed Atomic Operations

The Intel486 processor (and newer processors since) guarantees that the following basic memory operations will always be carried out atomically:

• Reading or writing a byte
• Reading or writing a word aligned on a 16-bit boundary
• Reading or writing a doubleword aligned on a 32-bit boundary

The Pentium processor (and newer processors since) guarantees that the following additional memory operations will always be carried out atomically:

• Reading or writing a quadword aligned on a 64-bit boundary
• 16-bit accesses to uncached memory locations that fit within a 32-bit data bus

The P6 family processors (and newer processors since) guarantee that the following additional memory operation will always be carried out atomically:

• Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line

Accesses to cacheable memory that are split across bus widths, cache lines, and page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be avoided.