testing - VHDL testbench 在仿真波形中获取 U

Question

我正在尝试使用黄金模型和 DUT 实现测试台，在这种情况下，我正在测试 4 位全加器。我总是在信号 s_dut 处变得不确定，而 s_gm 工作正常。我坚持了一段时间，我真的不知道问题出在哪里。

这是顶层模块:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity topmodule is
end topmodule;

architecture Behavioral of topmodule is

    component SomadorCompleto4bits_dut is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
             B : in  STD_LOGIC_VECTOR (3 downto 0);
             Cin : in  STD_LOGIC;
             S : out  STD_LOGIC_VECTOR (3 downto 0);
             Cout : out  STD_LOGIC);
    end component;

    component SomadorComOperador_golden_model is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
             B : in  STD_LOGIC_VECTOR (3 downto 0);
             S : out  STD_LOGIC_VECTOR (4 downto 0));
    end component;

    component testbench is
    port (s_dut, s_gm : in STD_LOGIC_VECTOR (4 downto 0);
            a, b : out STD_LOGIC_VECTOR (3 downto 0));
    end component;

    signal a, b : STD_LOGIC_VECTOR (3 downto 0);
    signal s_dut, s_gm : STD_LOGIC_VECTOR (4 downto 0); 


begin
    U0: SomadorCompleto4bits_dut port map(a, b, '0', s_dut (3 downto 0), s_dut(4));
    U1: SomadorComOperador_golden_model port map(a, b, s_gm);
    U2: testbench port map(s_dut, s_gm, a, b);
end Behavioral;

这里是测试平台:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity testbench is
    port (s_dut, s_gm : in STD_LOGIC_VECTOR (4 downto 0);
            a, b : out STD_LOGIC_VECTOR (3 downto 0));
end testbench;

architecture Behavioral of testbench is
begin
    process
        variable a_teste_in, b_teste_in : STD_LOGIC_VECTOR (3 downto 0);
    begin

        report "Iniciando teste..." severity NOTE;


        a_teste_in := "0000";
        b_teste_in := "0000";

        for i in 1 to 16 loop
            for j in 1 to 16 loop

                a <= a_teste_in;
                b <= b_teste_in;
                wait for 500 ns;

                assert (s_dut = s_gm) report "Falhou: i = " & integer'image(i) & " j = " & integer'image(j) severity ERROR;

                a_teste_in := a_teste_in + 1;

            end loop;

            b_teste_in := b_teste_in + 1;

        end loop;

        report "Teste finalizado!" severity NOTE;

        wait;

    end process;
end Behavioral;

我认为错误与以下行有关:

U0: SomadorCompleto4bits_dut port map(a, b, '0', s_dut (3 downto 0), s_dut(4));

---编辑:这是 DUT:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--DEVICE UNDER TEST--

entity SomadorCompleto is
     Port ( S : out  STD_LOGIC;
              Cout : out  STD_LOGIC;
              A : in  STD_LOGIC;
              B : in  STD_LOGIC;
              Cin : in  STD_LOGIC);
end SomadorCompleto;

architecture Behavioral of SomadorCompleto is

begin
    S <= A xor B xor Cin;
    Cout <= (A and B) or (A and Cin) or (B and Cin);
end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SomadorCompleto4bits_dut is
     Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
              B : in  STD_LOGIC_VECTOR (3 downto 0);
              Cin : in  STD_LOGIC;
              S : out  STD_LOGIC_VECTOR (3 downto 0);
              Cout : out  STD_LOGIC);
end SomadorCompleto4bits_dut;

architecture Behavioral of SomadorCompleto4bits_dut is

signal fio_c1, fio_c2, fio_c3 : STD_LOGIC;

component SomadorCompletoSimples is
    Port ( a : in  STD_LOGIC;
             b : in  STD_LOGIC;
             cin : in  STD_LOGIC;
             s : out  STD_LOGIC;
             cout : out  STD_LOGIC);
end component;

begin
    U0: SomadorCompletoSimples port map(A(0),B(0),'0',S(0),fio_c1);
    U1: SomadorCompletoSimples port map(A(1),B(1),fio_c1,S(1),fio_c2);
    U2: SomadorCompletoSimples port map(A(2),B(2),fio_c2,S(2),fio_c3);
    U3: SomadorCompletoSimples port map(A(3),B(3),fio_c3,S(3),Cout);
end Behavioral;

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提前致谢!

Answer 1

我只是忘了在 Somador Completo 上添加“样本”，因为两者是一样的