c - 超线程英特尔处理器和 C

Question

如果我在设计我的代码时不使用多线程范例，超线程会自动在逻辑内核上拆分负载，还是必须专门编写以利用其他内核，就像它必须用于物理内核一样核心？

Answer 1

根据@us2012 的建议，我从我的评论中将此发布在这里...

没有这样的魔法。 Superscalar CPU s，特别是OOO (Out Of Order execution) processors施展魔法 - 但那是在一个核心内。

相反，Hyperthreading可以被认为是(非常简化的)在一个完整核心之前的两条管道。

AMD Bulldozer CPUs有相似之处，但他们更进一步:整数核心也一分为二，但两个管道+整数核心共享一个浮点单元。这整体称为“模块”，有两个线程。

长话短说

超标量(来自维基)

A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.

乱序执行(来自维基)

In computer engineering, out-of-order execution (OoOE or OOE) is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay. In this paradigm, a processor executes instructions in an order governed by the availability of input data, rather than by their original order in a program. In doing so, the processor can avoid being idle while data is retrieved for the next instruction in a program, processing instead the next instructions which are able to run immediately.

超线程(来自...你知道在哪里...)

Hyper-threading (officially Hyper-Threading Technology or HT Technology, abbreviated HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on PC microprocessors. It first appeared in February 2002 on Xeon server processors and in November 2002 on Pentium 4 desktop CPUs.1 Later, Intel included this technology in Itanium, Atom, and Core 'i' Series CPUs, among others.

推土机(不是来自非维基)

Bulldozer is the first major redesign of AMD’s processor architecture since 2003, when the firm launched its K8 processors, and also features two 128-bit FMA-capable FPUs which can be combined into one 256-bit FPU. This design is accompanied by two integer clusters, each with 4 pipelines (the fetch/decode stage is shared). Bulldozer will also introduce shared L2 cache in the new architecture. AMD's marketing service calls this design a "Module". A 16-threads processor design would feature eight of these "modules",[7] but the operating system will recognize each "module" as two logical cores.