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c - 坚持使用 USART stm32f103rct6

转载 作者:太空宇宙 更新时间:2023-11-04 06:52:55 25 4
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我尝试连接 STMF103RCT6 的 USART(特别是 USART1 PA9-Tx 和 PA10-RX)。我已完成我的 PLL 配置以在 72MHz 下运行我的系统并且几乎没有问题。

我已将 stm32f103rct6 的 RX/TX 引脚连接到 USB 转串口 TX/RX,并在终端(软件:Tera Term)中以 115200 的波特率接收字符“A”。但它不起作用。

这是我的代码:

#include "stm32f10x.h"

#define HPRE_RESET_MASK ((uint32_t)0xFFFFFF0F)
#define PPRE2_RESET_MASK ((uint32_t)0xFFFFC7FF)
#define PPRE1_RESET_MASK ((uint32_t)0xFFFFF8FF)
#define PLLCLK_CONFIG_RESET_MASK ((uint32_t)0xFFC0FFFF)
#define SW_RESET_MASK ((uint32_t)0xFFFFFFFC)


#define LED_PORT_EN() ( RCC->APB2ENR |= RCC_APB2ENR_IOPDEN )
#define LED_PORT GPIOD

#define LED_MODE_BIT1 8
#define LED_MODE_BIT2 9
#define LED_CNF_BIT1 10
#define LED_CNF_BIT2 11


#define CNF_SET_PORTD(BIT1,BIT2) ( LED_PORT->CRL &= ~((1<<BIT1) | (1<<BIT2)) ) //General purpose output push-pull
#define MODE_SET_PORTD(BIT1,BIT2) ( LED_PORT->CRL |= (1<<BIT1) | (1<<BIT2) ) //Output mode, max speed 50 MHz.

#define SET_GPIO_BIT_PORTD(BIT) ( LED_PORT->BSRR = (1 << BIT) ) //For setting the Bit
#define RESET_GPIO_BIT_PORTD(BIT) ( LED_PORT->BSRR = ( (1 << BIT) << 16 ) ) //For Resseting Bit




void PLL_Config(void);
void Clock_Reset(void);
void HCLK_Config(uint32_t RCC_SYSCLK);
void PCLK2_Config(uint32_t RCC_HCLK);
void PCLK1_Config(uint32_t RCC_HCLK);
void PLLCLK_Config(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void SYSCLK_Config(uint32_t RCC_SYSCLKSource);
void Delay(int ms);
void Led_Init(void);
void Blink_Led(int ms);
void Transmit_Char(char data);


int main(void)
{

PLL_Config();
Led_Init();
//RCC configure for PORTA
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;
/*for uart 1*/
GPIOA->CRH |= GPIO_CRH_MODE9; //Configure TX PORTA 9 push pull
GPIOA->CRH &= ~(GPIO_CRH_CNF9);

GPIOA->CRH |= GPIO_CRH_MODE10; //Configure RX PORTA 10 push pull
GPIOA->CRH &= ~(GPIO_CRH_CNF10);

RCC->APB2ENR |= RCC_APB2ENR_USART1EN; //enable clock for usart
USART1->BRR = 0x271; //set Baud mantisa 0x27 fraction 0x1
/*enable usart, enable RX,TX */
USART1->CR1 = USART_CR1_RE | USART_CR1_TE | USART_CR1_UE;

while(1)
{
Transmit_Char('A'); //transmit a data
Delay(1000);
Blink_Led(1000);
}
}


/** @breif: Transmit a character
* @param: the character to be transmitted
* @retVal: None
*/

void Transmit_Char(char data)
{
while (!(USART1->SR & USART_SR_TXE));
USART1->DR = data & 0xFF;
}


/** @breif: For wait and doing nothing i.e for delay
* @param: delaya time
* @retVal: None
*/


void Delay(int ms)
{
int i,j;
for (i = 0; i < ms; ++i) {
for (j = 0; j < 1000; ++j);
}
}


/** @breif: Initalize GPIO For Led
* @param: None
* @retVal: None
*/


void Led_Init()
{
LED_PORT_EN(); //Enable RCC for Led Port
CNF_SET_PORTD(LED_CNF_BIT1,LED_CNF_BIT2); //SET CNF General purpose output push-pull
MODE_SET_PORTD(LED_MODE_BIT1,LED_MODE_BIT2); //SET MODE Output mode, max speed 50 MHz.
}


/** @breif: Blink Led Placed in PORT D Pin 2
* @param: Delay for each state(ON/OFF)
* @retVal: None
*/


void Blink_Led(int ms)
{
RESET_GPIO_BIT_PORTD(2); //Make Led High
Delay(ms); //wait
SET_GPIO_BIT_PORTD(2); //Make Led Low
Delay(ms); //wait
}

/** @breif: Configure PLL 72 MHz
* @param: None
* @retVal: None
*/

void PLL_Config(void)
{
Clock_Reset(); //RESET Clock
RCC->CR |= RCC_CR_HSEON; //ENABLE HSE

/* wait till HSE Ready */
while ( !( RCC->CR & RCC_CR_HSERDY ));

/* Doubt: Enable Prefetch Buffer */
/* Doubt: Flash 2 wait state */

HCLK_Config(RCC_CFGR_HPRE_DIV1); //configure HCLK AHB clock
PCLK2_Config(RCC_CFGR_PPRE2_DIV1); //cofigure PCLK2 APB2 clock
PCLK1_Config(RCC_CFGR_PPRE1_DIV2); //configure PCLK1 APB1 clock
PLLCLK_Config(RCC_CFGR_PLLSRC, RCC_CFGR_PLLMULL9); //configure PLLCLK 72MHz

RCC->CR |= RCC_CR_PLLON; //ENABLE PLL

/* Wait till PLL is Ready */
while (!(RCC->CR & RCC_CR_PLLRDY));

SYSCLK_Config(RCC_CFGR_SW_PLL);

/* wait till PLL is used as system clock */
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL));

}


/** @breif: Select PLL as system clock source
* @param: RCC_CFGR_SW_PLL = ((uint32_t)0x00000002)
* @retVal: None
*/

void SYSCLK_Config(uint32_t RCC_SYSCLKSource)
{
uint32_t tmpreg = 0;

tmpreg = RCC->CFGR;
/* Clear SW[1:0] bits */
tmpreg &= SW_RESET_MASK;
/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
tmpreg |= RCC_SYSCLKSource;
/* Store the new value */
RCC->CFGR = tmpreg;
}



/** @breif: Set PCLK1 = HCLK/2
* HCLK divided by 2
* @param: RCC_CFGR_PLLSRC = ((uint32_t)0x00010000)
* @param: RCC_CFGR_PLLMULL9 = ((uint32_t)0x001C0000)
* @retVal: None
*/
void PLLCLK_Config(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
{
uint32_t tmpreg = 0;

tmpreg = RCC->CFGR;
/* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
tmpreg &= PLLCLK_CONFIG_RESET_MASK;
/* Set the PLL configuration bits */
tmpreg |= RCC_PLLSource | RCC_PLLMul;
/* Store the new value */
RCC->CFGR = tmpreg;
}


/** @breif: Set PCLK1 = HCLK/2
* HCLK divided by 2
* @param: RCC_CFGR_PPRE1_DIV2 = ((uint32_t)0x00000400)
* @retVal: None
*/

void PCLK1_Config(uint32_t RCC_HCLK)
{
uint32_t tmpreg = 0;

tmpreg = RCC->CFGR;
/* Clear PPRE1[2:0] bits */
tmpreg &= PPRE1_RESET_MASK;
/* Set PPRE1[2:0] bits according to RCC_HCLK value */
tmpreg |= RCC_HCLK;
/* Store the new value */
RCC->CFGR = tmpreg;
}




/** @breif: Set PCLK2 = HCLK
* HCLK not divided
* @param: RCC_CFGR_PPRE2_DIV1 = ((uint32_t)0x00000000)
* @retVal: None
*/

void PCLK2_Config(uint32_t RCC_HCLK)
{
uint32_t tmpreg = 0;

tmpreg = RCC->CFGR;
/* Clear PPRE2[2:0] bits */
tmpreg &= PPRE2_RESET_MASK;
/* Set PPRE2[2:0] bits according to RCC_HCLK value */
tmpreg |= RCC_HCLK;
/* Store the new value */
RCC->CFGR = tmpreg;
}


/** @breif: Set HCLK = SYSCLK
* SYSCLK not divided
* @param: RCC_CFGR_HPRE_DIV1 = ((uint32_t)0x00000000)
* @retVal: None
*/

void HCLK_Config(uint32_t RCC_SYSCLK)
{
uint32_t tmpreg = 0;

tmpreg = RCC->CFGR;
/* Clear HPRE[3:0] bits */
tmpreg &= HPRE_RESET_MASK;
/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
tmpreg |= RCC_SYSCLK;
/* Store the new value */
RCC->CFGR = tmpreg;
}



/** @breif: Resets the Clock
* @param: None
* @retVal: None
*/
void Clock_Reset(void)
{
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;

/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (uint32_t)0xF0FF0000;

/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;

/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;

/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;

/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
}

我对这段代码几乎没有怀疑。

  1. 小数波特率生成:

    给出的公式是:

    Tx/Rx 波特率 = fclk/(16 * USARTDIV)

    fclk(在 pll 设置后将为 72MHz):72MHz

    所需的 Tx/Rx 波特率是:115200

    所以 USARTDIV = fclk/(16*baud)

    即 USARTDIV = 72000000/(16*115200) = 39.0625(在表 192 中给出。编程波特率的误差计算)

    然后有一个示例问题(示例 2),它说将 USARTDIV 编程为 39.0625(您的 USARTDIV)

    DIV_Fraction = 16*0d0.0625 = 0d1 = 0x1

    DIV_Mantissa = 尾数 (0d39.0625) = 0d39 = 0x27

    然后,USART_BRR = 0x271

    我已经在我的 USART_BRR 寄存器上使用了这个值,但没有得到正确的值。

  2. Usart tx 的代码是否正确?

任何建议都会很有帮助。因为终端中没有显示任何内容,即 usart 不工作

提前致谢

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