c - STM32F7 Discovery - USB FS主机/设备模式检测

Question

STM32F723IEK6 探索板具有全速 USB 接口(interface)。我试图初始化它是徒劳的。永远不会从主机接收到复位信号，并且不会设置相应的中断标志。

FS接口(interface)是OTG。它应该检测 VBUS 电压和 ID 引脚的状态，以确定它是作为主机连接还是作为设备连接。在设备模式下，VBUS 应由主机提供，ID 引脚应断开连接并拉高。当设备检测到连接时，它应该拉动 DP 引脚以指示与主机的连接。然后主机通过将数据线拉低来发送RESET信号。这是理论。

看来开发板没有将 DP 线拉高。在启用 VBUS 检测的默认 OTG 配置(如下面的程序)中，只有 CIDSCHG(ID 更改)、SRQINT( session )和 SOF 位曾在 GINTSTS 寄存器中设置。 CMOD 位为零，指示设备模式。 ID 线似乎很低，即使未连接电缆也是如此。

我在 AF 10 模式 (OTG FS) 中配置了适当的引脚(A9、A10、A11、A12)。然而，这可能是不必要的，因为 FS PHY 似乎直接连接到引脚，绕过了 GPIO 多路复用器(不确定)。

我试过强制进入设备模式并禁用 VBUS 检测，但这没有任何效果，也尝试从 GPIO 拉起 ID 线。

我以前在 STM32F4 板上运行过相同的代码，但没有出现此类问题。

我想了解为什么连接检测不起作用。

代码如下，啰嗦了，有时钟、GPIO、USB初始化代码，一些辅助功能省略。

STM32F72x 引用手册(15MB!)http://www.st.com/resource/en/reference_manual/dm00305990.pdf

数据表 http://www.st.com/resource/en/datasheet/DM00330506.pdf

开发板手册http://www.st.com/resource/en/user_manual/dm00342318.pdf

#include "stm32f7xx.h"

#define PLL_M 25
#define PLL_N 336
#define PLL_P 0
#define PLL_Q 7
#define SYS_FREQ 168000000

void rcc_config(void)
{
    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
    PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS_Msk)
            | PWR_CR1_VOS_1;
    RCC->CR |= RCC_CR_HSEON;
    while ((RCC->CR & RCC_CR_HSERDY) == 0);
    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (PLL_P << 16) | RCC_PLLCFGR_PLLSRC_HSE | (PLL_Q << 24);
    RCC->CR |= RCC_CR_PLLON;
    RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE_Msk | RCC_CFGR_PPRE1_Msk | RCC_CFGR_PPRE2_Msk))
            | RCC_CFGR_HPRE_DIV1
            | RCC_CFGR_PPRE2_DIV2
            | RCC_CFGR_PPRE1_DIV4;
    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN | FLASH_ACR_LATENCY_5WS;
    while ((RCC->CR & RCC_CR_PLLRDY) == 0);
    while ((PWR->CSR1 & PWR_CSR1_VOSRDY) == 0);
    RCC->CFGR &= RCC_CFGR_SW;
    RCC->CFGR |= RCC_CFGR_SW_PLL;
    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
}

#define GPIO_OTYPE_PP 0
#define GPIO_OTYPE_OD 1
#define GPIO_PULLUP   1

void gpio_config_mode(GPIO_TypeDef* gpio, unsigned pin, unsigned mode)
{
    gpio->MODER = (gpio->MODER & ~(3u << (2 * pin))) | (mode << (2 * pin));
}
void gpio_config_in(GPIO_TypeDef* gpio, unsigned pin)
{
    gpio_config_mode(gpio, pin, 0);
}
void gpio_config_out(GPIO_TypeDef* gpio, unsigned pin, unsigned otype, unsigned ospeed)
{
    gpio_config_mode(gpio, pin, 1);
    gpio->OTYPER  = (gpio->OTYPER  & ~(1u << (1 * pin))) | (otype  << (1 * pin));
    gpio->OSPEEDR = (gpio->OSPEEDR & ~(3u << (2 * pin))) | (ospeed << (2 * pin));
}
void gpio_config_af(GPIO_TypeDef* gpio, unsigned pin, unsigned af)
{
    gpio_config_mode(gpio, pin, 2);
    unsigned pin_group = pin >> 3;
    unsigned pin_offset = pin & 7;
    gpio->AFR[pin_group] = (gpio->AFR[pin_group] & ~(0xf << (pin_offset * 4)))
            | (af << (pin_offset * 4));
}
void gpio_config_pullup(GPIO_TypeDef* gpio, unsigned pin, unsigned pupd)
{
    gpio->PUPDR = (gpio->PUPDR   & ~(3u << (2 * pin))) | (pupd   << (2 * pin));
}

USB_OTG_GlobalTypeDef *usb = USB_OTG_FS;
USB_OTG_DeviceTypeDef *usb_dev = (USB_OTG_DeviceTypeDef *)(USB_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE);

void usb_config(void)
{
    /* The application must program this register before starting any transactions
     * on either the AHB or the USB. Do not make changes to this register after
     * the initial programming. */
    usb->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; // TODO: no effect for F7, read-only bit
//  usb->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
    /* After setting the force bit, the application must wait at least * 25 ms
     * before the change takes effect. */
    delay_ms(25);

    // USB core reset
    while ((usb->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
    usb->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
    while ((usb->GRSTCTL & USB_OTG_GRSTCTL_CSRST) != 0);
    delay_us(1); // actually, 3 PHY clocks

    usb_dev->DCFG = USB_OTG_DCFG_DSPD_0 | USB_OTG_DCFG_DSPD_1; // full speed
//  usb->GAHBCFG = 0;
//  usb->PCGCTL = 0;
    usb->GCCFG |= USB_OTG_GCCFG_VBDEN; // VBUS detection
    usb->GCCFG |= USB_OTG_GCCFG_PWRDWN; // enable PHY

/// usb->GINTSTS= 0xFFFFFFFF;
//  usb->GINTMSK = 0;
//  usb->GINTSTS = 0xFFFFFFFF;
//  usb->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
}

void usb_poll(void)
{
    uint32_t intsts = usb->GINTSTS;
    if (intsts & USB_OTG_GINTSTS_USBRST)
        usb->GINTSTS = USB_OTG_GINTSTS_USBRST;
    if (intsts & USB_OTG_GINTSTS_RSTDET)
        usb->GINTSTS = USB_OTG_GINTSTS_RSTDET;
    if (intsts & USB_OTG_GINTSTS_ENUMDNE)
        usb->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
    if (intsts & USB_OTG_GINTSTS_CIDSCHG)
        usb->GINTSTS = USB_OTG_GINTSTS_CIDSCHG;
    if (intsts & USB_OTG_GINTSTS_SRQINT)
        usb->GINTSTS = USB_OTG_GINTSTS_SRQINT;
}

#define LED_PIN 5
#define USB_AF 10

int main()
{
    rcc_config();

    SysTick->LOAD = 0xffffffu;
    SysTick->VAL = 0;
    SysTick->CTRL = 5;

    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
    gpio_config_out(GPIOA, LED_PIN, GPIO_OTYPE_PP, 0);
    gpio_config_af(GPIOA,  9, USB_AF); // VBUS_DET
    gpio_config_af(GPIOA, 10, USB_AF); // ID
    gpio_config_af(GPIOA, 11, USB_AF); // DM
    gpio_config_af(GPIOA, 12, USB_AF); // DP

    RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
    usb_config();
    while (1)
        usb_poll();
}

Answer 1

当然。

OTG_FS_DCTL 寄存器:

Bit 1

SDIS:

Soft disconnect The application uses this bit to signal the USB OTG core to perform a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. 0: Normal operation. When this bit is cleared after a soft disconnect, the core generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. 1: The core generates a device disconnect event to the USB host.

摘自STM32F411手册:

Reset value: 0x0000 0000

摘自STM32F723手册:

Reset value: 0x0000 0002

除非应用程序修改了复位值，否则 STM32F7 USB block 以“软断开”状态启动，而 STM32F4 会在检测到 VBUS 时立即尝试连接。文档(例如第 32.6.2 节外围状态)根本没有提到这个事实。

在我的例子中，清除 SDIS 位启用成功的连接握手。