algorithm - Verilog GCD 执行错误

Question

回复:编辑

我能够解决这个问题并继续使用我编写的测试平台来模拟波形，不幸的是我的主函数没有生成波形。

我的测试台:

`timescale 1ns/1ps
module gcd_test();

reg [15:0] a,b;
reg clk, rst;

gcd uut(a,b,clk,rst);

initial begin

rst = 1;
a = 16'b0000000000001100;
b = 16'b0000000000000011;

end

initial begin
rst = 0;
end

always begin
#50
clk = 0;
#50
clk = 1;
end


endmodule

我的输出波形是几个 zzzz(好像我的代码执行起来很无聊)。我检查了测试台的输出，它很好，但我的主要功能并非如此。输出波不是它应该的那样。我的测试台或从我的测试台到主要的值的解析又是错误的吗？

TIA。

++++++++++++++++++++++++++++++++++++++++++++++++

我正在尝试使用 Verilog HDL 执行 GCD 函数，并且我正在使用一个简单的算法来执行此操作。然而，我在执行过程中不断遇到一些错误。

我的代码:

module gcd(
input [15:0] a,
input [15:0] b,
input clk,
input rst);

reg [15:0] ra;
reg [15:0] rb;
reg [15:0] gcd;
reg done;
reg [2:0] state;
parameter start = 2'h1;
parameter check = 2'h2;
parameter comp = 2'h3;
parameter lastend = 2'h4;


always @ (posedge clk or posedge rst)
if (rst)
begin
    ra <= 16'h0;
    ra <= 16'h0;
    gcd <= 16'h0;
    state <= start;
end

else begin
    case(state)
        start: //status 0
                begin
                    ra <= a;
                    rb <= b;
                    state <= check;
                end
        check:  //Status 1
                begin
                    if ((ra == 16'h0) || (ra == 16'h0))
                    begin
                        state <= lastend;
                    end
                    else begin
                        state <= comp;
                    end
                end
        comp: //status 2
                begin
                    if(ra > rb) //Compare ra and rb
                    begin
                        ra = ra - rb;
                        if((ra < 16'h0) || (rb < 16'h0)) //Compare ra and rb and if either has become 0
                        begin
                            done = 1'h0;
                            state <= lastend;
                        end
                        else begin
                            state <= comp;
                            gcd <= ra;
                        end
                    end
                    else if (rb > ra) //Compare ra and rb
                    begin
                        rb = rb - ra;
                        if((ra < 16'h0) || (rb < 16'h0))//Compare ra and rb and if either has become 0
                        begin
                            done <= 1'h0;
                            state <= lastend;
                        end
                        else begin
                            state <= comp;
                            gcd <= ra;
                        end
                    end
                    else if(ra == rb) //Finally gcd found ra == rb
                        begin
                            gcd <= ra;
                            done <= 1'h0;
                            state <= start;
                        end
        lastend: //status 3
                        begin
                            gcd <= 16'h0;
                            done <= 1'h0;
                        end

    endcase
end
endmodule                       

Error (10170): Verilog HDL syntax error at gcd.v(85) near text "endcase"; expecting "end"

或者

Error (10163): Verilog HDL error at gcd.v(53): illegal name "lastend" used in expression
Error (10163): Verilog HDL error at gcd.v(66): illegal name "lastend" used in expression

在代码上附加了一个额外的结尾。

此外，我回溯了代码，似乎发现所有的开始都有适当的结束。

任何建议都非常有帮助。

Answer 1

这开始了:

        comp: //status 2
                begin

似乎没有匹配的结尾。