algorithm - DSP/FPGA 相位累加器如何工作？

Question

我正在查看相位累加器的代码，我一定是个傻瓜，因为我不明白。代码很简单:

  Every Clock Tick do:    accum = accum + NCO_param;    return accum;

accum 是一个 32 位寄存器。显然，在某些时候它会翻转。

我的问题实际上是:这与灵态有什么关系？

Answer 1

This article可能有帮助。

在运行步骤中，计数器(恰本地称为相位累加器)被指示在每个脉冲上从频率引用前进一定的增量。相位累加器的输出(相位)用于依次选择数据表中的每一项。最后，DAC 将此数据序列转换为模拟波形。

In the running step, the counter (properly called the phase accumulator) is instructed to advance by a certain increment on each pulse from the frequency reference. The output of the phase accumulator (the phase) is used to select each item in the data table in turn. Finally, the DAC converts this sequence of data to an analogue waveform. To generate a periodic waveform, the circuit is set up so that one pass through the table takes a time equal to the period of the waveform. For example, if the reference frequency is 1 MHz, and the table contains 1000 entries, then a complete pass through the table with a phase increment of 1 will take 1000 / 1 MHz = 1 ms, so the frequency of the output waveform will be 1/(1 ms) = 1 kHz.

This system can generate a higher output frequency simply by increasing the phase increment so that the counter runs through the table more quickly. In the example above, the phase increment is equal to 1, so the next possible frequency is obtained by setting the increment to 2, resulting in a doubling of output frequency. To obtain a finer control of frequency than this, the standard phase increment can be set to, say, 10. This then allows slightly higher or lower output frequencies. For example, increasing the increment to 11 would increase the output frequency by 10%, and reducing it to 9 would decrease the output frequency by the same proportion. The more precision required over the frequency, the more bits are needed in the counter.