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我有电路原理图的网表(子电路的集合),通常是由一些 SPICE 模拟器创建的。它通常具有层次结构(顶级子电路调用或实例化不同的子电路并通过引脚定义它们之间的一些连接)。示例网表如下所示:
subckt AN2D0 A1 A2 VDD VSS Z
M_u2 (net5 A2 VDD VDD) pch
M_u1 (net5 A1 VDD VDD) pch
M_u3 (Z net5 VDD VDD) pch
M_u4 (net17 A2 VSS VSS) nch
M_u2 (Z net5 VSS VSS) nch
ends AN2D0
subckt LS_RX_CONTROLLER VDD VSS burst_start_or_sys burst_start_out pd pd_pwm_det pd_pwm_det_TII std_by std_by_or_sys sys_en sys_out
I2 (burst_start_or_sys std_by VDD VSS burst_start_out) AN2D2
I1 (net22 std_by_bar VDD VSS sys_out) AN2D2
I5 (net022 pd VDD VSS pd_pwm_det) OR2D2
I10 (net026 pd VDD VSS std_by_or_sys) NR2D2
I9 (sys_en std_by VDD VSS net026) NR2D0
I6 (std_by VDD VSS std_by_bar) INVD0
I3 (pd_pwm_det_TII net037 VDD VSS net022) OR2D0
I11 (sys_en std_by VDD VSS net037) OR2D0
I0 (burst_start_or_sys sys_en VDD VSS net22) AN2D0
ends LS_RX_CONTROLLER
现在可以在不同的层次结构中实例化相同的子电路。每个被调用的子电路都在调用子电路之前定义。这种图称为Directed Acyclic GRAPH。我已经从网表中创建了一个自引用哈希表以节省空间。如果子电路正在调用某个子电路实例,则它指向引脚。在最后一层,我们将得到一个 MOSFET D 或 S 或 G 或 B 节点(因为已定义 AN2D0 子电路)。如果任何网络(实例引脚之间的连接)从层次结构(除了调用子电路,例如 net5)到父调用子电路,它被称为引脚(例如 Z),并且将始终列在当前的子电路定义行中通过其名称 (subckt AN2D0 A1 A2 VDD VSS Z)。我创建了一个哈希的哈希。
GRAPH --> subckt1--->p1
p2
net1
net2
subckt2--->p1
p2
net1
net2
subckt3--->p1 ---->I1.subckt1.p1--->pointing to value of p1 key of subckt1.
I2.subckt1.p2
p2
net1
net2
对于目前的情况,GRAPH 看起来像:
the name of subcircuit-->AN2D0
name of pin or net-->Z
name of instant connected to it-->M_u2.nch.D
name of instant connected to it-->M_u3.pch.D
name of pin or net-->VDD
name of instant connected to it-->M_u1.pch.S
name of instant connected to it-->M_u1.pch.B
name of instant connected to it-->M_u2.pch.S
name of instant connected to it-->M_u3.pch.S
name of instant connected to it-->M_u2.pch.B
name of instant connected to it-->M_u3.pch.B
name of pin or net-->A1
name of instant connected to it-->M_u3.nch.G
name of instant connected to it-->M_u1.pch.G
name of pin or net-->VSS
name of instant connected to it-->M_u2.nch.S
name of instant connected to it-->M_u4.nch.B
name of instant connected to it-->M_u2.nch.B
name of instant connected to it-->M_u3.nch.B
name of instant connected to it-->M_u4.nch.S
name of pin or net-->net5
name of instant connected to it-->M_u3.nch.D
name of instant connected to it-->M_u3.pch.G
name of instant connected to it-->M_u1.pch.D
name of instant connected to it-->M_u2.pch.D
name of instant connected to it-->M_u2.nch.G
name of pin or net-->A2
name of instant connected to it-->M_u4.nch.G
name of instant connected to it-->M_u2.pch.G
name of pin or net-->net17
name of instant connected to it-->M_u3.nch.S
name of instant connected to it-->M_u4.nch.D
the name of subcircuit-->LS_RX_CONTROLLER
name of pin or net-->burst_start_or_sys
name of instant connected to it-->I2.AN2D2.A1
M_u3.nch.G
M_u1.pch.G
name of instant connected to it-->I0.AN2D0.A1
M_u3.nch.G
M_u1.pch.G
name of pin or net-->burst_start_out
name of instant connected to it-->I2.AN2D2.Z
M_u2.nch.D
M_u3.pch.D
name of pin or net-->net037
name of instant connected to it-->I11.OR2D0.Z
M_u2.nch.D
M_u3.pch.D
name of instant connected to it-->I3.OR2D0.A2
M_u3.nch.G
M_u1.pch.G
name of pin or net-->net026
name of instant connected to it-->I10.NR2D2.A1
M_u4.nch.G
M_u2.pch.G
name of instant connected to it-->I9.NR2D0.ZN
M_u3.nch.D
M_u2.pch.D
M_u4.nch.D
name of pin or net-->std_by
name of instant connected to it-->I9.NR2D0.A2
M_u3.nch.G
M_u1.pch.G
name of instant connected to it-->I6.INVD0.I
M_u3.pch.G
M_u2.nch.G
name of instant connected to it-->I2.AN2D2.A2
M_u4.nch.G
M_u2.pch.G
name of instant connected to it-->I11.OR2D0.A2
M_u3.nch.G
M_u1.pch.G
name of pin or net-->sys_en
name of instant connected to it-->I11.OR2D0.A1
M_u4.nch.G
M_u2.pch.G
name of instant connected to it-->I0.AN2D0.A2
M_u4.nch.G
M_u2.pch.G
name of instant connected to it-->I9.NR2D0.A1
M_u4.nch.G
M_u2.pch.G
name of pin or net-->VDD
name of instant connected to it-->I2.AN2D2.VDD
M_u1.pch.S
M_u1.pch.B
M_u2.pch.S
M_u3.pch.S
M_u2.pch.B
M_u3.pch.B
name of instant connected to it-->I10.NR2D2.VDD
M_u1.pch.S
M_u1.pch.B
M_u2.pch.B
name of instant connected to it-->I0.AN2D0.VDD
M_u1.pch.S
M_u1.pch.B
M_u2.pch.S
M_u3.pch.S
M_u2.pch.B
M_u3.pch.B
name of instant connected to it-->I6.INVD0.VDD
M_u3.pch.S
M_u3.pch.B
name of instant connected to it-->I9.NR2D0.VDD
M_u1.pch.S
M_u1.pch.B
M_u2.pch.B
name of instant connected to it-->I1.AN2D2.VDD
M_u1.pch.S
M_u1.pch.B
M_u2.pch.S
M_u3.pch.S
M_u2.pch.B
M_u3.pch.B
name of instant connected to it-->I11.OR2D0.VDD
M_u1.pch.S
M_u1.pch.B
M_u3.pch.S
M_u2.pch.B
M_u3.pch.B
name of instant connected to it-->I3.OR2D0.VDD
M_u1.pch.S
M_u1.pch.B
M_u3.pch.S
M_u2.pch.B
M_u3.pch.B
name of instant connected to it-->I5.OR2D2.VDD
M_u1.pch.S
M_u1.pch.B
M_u3.pch.S
M_u2.pch.B
M_u3.pch.B
name of pin or net-->sys_out
name of instant connected to it-->I1.AN2D2.Z
M_u2.nch.D
M_u3.pch.D
name of pin or net-->net022
name of instant connected to it-->I3.OR2D0.Z
M_u2.nch.D
M_u3.pch.D
name of instant connected to it-->I5.OR2D2.A1
M_u4.nch.G
M_u2.pch.G
name of pin or net-->pd_pwm_det_TII
name of instant connected to it-->I3.OR2D0.A1
M_u4.nch.G
M_u2.pch.G
name of pin or net-->std_by_or_sys
name of instant connected to it-->I10.NR2D2.ZN
M_u3.nch.D
M_u2.pch.D
M_u4.nch.D
name of pin or net-->net22
name of instant connected to it-->I0.AN2D0.Z
M_u2.nch.D
M_u3.pch.D
name of instant connected to it-->I1.AN2D2.A1
M_u3.nch.G
M_u1.pch.G
name of pin or net-->pd
name of instant connected to it-->I10.NR2D2.A2
M_u3.nch.G
M_u1.pch.G
name of instant connected to it-->I5.OR2D2.A2
M_u3.nch.G
M_u1.pch.G
name of pin or net-->std_by_bar
name of instant connected to it-->I6.INVD0.ZN
M_u2.nch.D
M_u3.pch.D
name of instant connected to it-->I1.AN2D2.A2
M_u4.nch.G
M_u2.pch.G
name of pin or net-->VSS
name of instant connected to it-->I11.OR2D0.VSS
M_u3.nch.S
M_u2.nch.S
M_u4.nch.B
M_u2.nch.B
M_u3.nch.B
M_u4.nch.S
name of instant connected to it-->I5.OR2D2.VSS
M_u3.nch.S
M_u4.nch.B
M_u2.nch.S
M_u2.nch.B
M_u3.nch.B
M_u4.nch.S
name of instant connected to it-->I3.OR2D0.VSS
M_u3.nch.S
M_u2.nch.S
M_u4.nch.B
M_u2.nch.B
M_u3.nch.B
M_u4.nch.S
name of instant connected to it-->I6.INVD0.VSS
M_u2.nch.S
M_u2.nch.B
name of instant connected to it-->I0.AN2D0.VSS
M_u2.nch.S
M_u4.nch.B
M_u2.nch.B
M_u3.nch.B
M_u4.nch.S
name of instant connected to it-->I2.AN2D2.VSS
M_u2.nch.S
M_u4.nch.B
M_u2.nch.B
M_u3.nch.B
M_u4.nch.S
name of instant connected to it-->I1.AN2D2.VSS
M_u2.nch.S
M_u4.nch.B
M_u2.nch.B
M_u3.nch.B
M_u4.nch.S
name of instant connected to it-->I9.NR2D0.VSS
M_u3.nch.S
M_u4.nch.B
M_u3.nch.B
M_u4.nch.S
name of instant connected to it-->I10.NR2D2.VSS
M_u3.nch.S
M_u4.nch.B
M_u3.nch.B
M_u4.nch.S
name of pin or net-->pd_pwm_det
name of instant connected to it-->I5.OR2D2.Z
M_u2.nch.D
M_u3.pch.D
在此之后,将给出一个子电路名称和一个相同的引脚,它们可以从任何级别层次结构中实例化,我们必须找到父级,即追溯父级,直到网络作为引脚被拉起。然后将所有叶子(MOSFETS D or G or S or B pin)压回。
请建议哪种算法最适合这种情况,以及将它们存储在自引用哈希表中是否有效。
最佳答案
根据我的经验,最好使用索引过程来生成图形中节点的唯一标识,然后创建一个平面散列,其中键是这个 id。使用 id 创建链接。例如:
a => b, b => c, c => d, d => a
翻译成
% 图 = (
一个 => { 内容 => ...,
链接 => [ b ] },
b => { 内容 => ...,
链接 => [ c ] },
c => { 内容 => ...,
链接 => [ d ] },
d => { 内容 => ...,
链接=> [ a ] }
);
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