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我试图在一个文件的两个特定行之间复制代码,并将其粘贴到另一个文件中相同的两个相应行之间。
例如我有两个文件test.sv_old 和test.sv。我想将代码从 test.sv_old 文件复制到下面两行之间的 test.sv
第 1 行:“//功能规范的开始”
第 2 行:“//如果没有供应,输出设置为 0。根据需要取消注释。”
这是 test.sv_old 文件的内容:
`include "def.sv"
/PRIMARY
/SECONDARY
/TERTIARY
/UNASSIGNED
module abc ( );
we want to see this too
//Start of functional specification here
//Functional cell instantiation
abc_real Inst0 (.z1(int_z1),
.z2(int_z2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // abc
`include "def.sv"
/PRIMARY
/SECONDARY
/TERTIARY
/UNASSIGNED
module xyz ( );
//Start of functional specification here
//Functional cell instantiation
xyz_real Inst0 (.y1(int_y1),
.y2(int_y2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // xyz
`include "def.sv"
/PRIMARY
/SECONDARY
/TERTIARY
/UNASSIGNED
module lmn ( );
//Start of functional specification here
//Functional cell instantiation
lmn_real Inst0 (.x1(int_x1),
.x2(int_x2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // lmn
这是我的 test.sv 文件:
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module abc ( );
keep this code untouched
no change needed here
//Start of functional specification here
//Functional cell instantiation
some garbage
here
just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // abc
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module xyz ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
some garbage
here and there
why not just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // xyz
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module lmn ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
some garbage
here and there
why not just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // lmn
我试过下面的代码,但它没有给我所需的准确输出:
import sys,re,os
rf_SVFile=open(sys.argv[1],"r")
wtstring = ""
wtindex = 0
copy = False
write = False
print("Copying instantiation code from {} to new SV file {}".format(rf_SVFile.name,sys.argv[2]))
for vline in rf_SVFile:
if vline.strip() == "//Start of functional specification here" and copy == False:
copy = True
elif vline.strip() == "// Outputs set to 0 if no supply. Uncomment as needed.":
copy = False
elif copy:
wtstring = wtstring + vline # wtstring has the functional code between two lines which you want to write to .sv file
with open(sys.argv[2], "r+") as wf_NewSVFile:
insert = False
contents = wf_NewSVFile.readlines()
for index, svline in enumerate(contents):
if svline.strip() == "// Outputs set to 0 if no supply. Uncomment as needed.":
wtindex = index
insert = True
break
contents.insert(wtindex,wtstring) # contents has complete code in list format, instantantiation code is copied from SV file to new SV File
stringContents = "".join(contents) # convert list into string in order to write it to .sv file
if insert:
wf_NewSVFile.seek(0, 0)
wf_NewSVFile.write(str(stringContents))
else:
print(
'Warning: No "/ Outputs set to 0 if no supply. Uncomment as needed." line found in {}, hence code is not being copied to new SV file',NewSVFile)
这里是修改后的 test.sv 文件,由上面的代码生成:
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module abc ( );
keep this code untouched
no change needed here
//Start of functional specification here
//Functional cell instantiation
some garbage
here
just replace this
//Functional cell instantiation
abc_real Inst0 (.z1(int_z1),
.z2(int_z2),
.a1(reg_a1));
//Functional cell instantiation
xyz_real Inst0 (.y1(int_y1),
.y2(int_y2),
.a1(reg_a1));
//Functional cell instantiation
lmn_real Inst0 (.x1(int_x1),
.x2(int_x2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // abc
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module xyz ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
some garbage
here and there
why not just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // xyz
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module lmn ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
some garbage
here and there
why not just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // lmn
谁能解释一下,我做错了什么?谢谢。
最佳答案
使用一些关键字创建索引,然后加入切片应该可以解决问题。
with open('test.sv') as f:
content = f.readlines()
with open('test_old.sv') as f:
content_2 = f.readlines()
cp_s = [i for i, v in enumerate(content_2) if 'Functional' in v]
cp_end = [i for i, v in enumerate(content_2) if 'Outputs' in v]
dest_s = [i for i, v in enumerate(content) if 'Functional' in v]
dest_end = [i for i, v in enumerate(content) if 'Outputs' in v]
new = content[:dest_s[0]] + content_2[cp_s[0]: cp_end[0]] + content[dest_end[0]: dest_s[1]] +
content_2[cp_s[1]:]
with open('fixed.sv', 'w') as f:
f.write(''.join(new))
输出:
chrx@chrx:~/python/stackoverflow/10.11$ cat fixed.sv
module abc ( );
keep this code untouched
no change needed here
//Start of functional specification here
//Functional cell instantiation
abc_real Inst0 (.z1(int_z1),
.z2(int_z2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // abc
module xyz ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
xyz_real Inst0 (.z1(int_z1),
.z2(int_z2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // xyz
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