c# - 无法在 C# 应用程序中为我的线程使用多个处理器组

Question

根据 MSDN documentation和 Stephen Toub answer ，我的 C# 应用程序应该使用每个处理器组的每个逻辑处理器，因为它是根据需要配置的(请参阅下面我的 App.config)。

我在具有 NUMA 架构的 Windows Server 2012 上运行我的应用程序:2 x [cpu Xeon E5-2697 v3，14 个内核，每个内核都激活了超线程] => 2 x 14 x 2 = 56 个逻辑处理器。

我的应用程序从“线程类”或“Parallel.For”启动 80 个线程，在这两种情况下，它只需要 28 个逻辑处理器，全部来自同一个处理器组。

为什么任务调度器只在一个处理器组上分配我的线程？

我的代码可在 GitHub 获得或者可以在我的 Home website 下载可执行文件

我已经在 social.msdn.microsoft.com 上问过这个问题了没有任何答案。

• 2015-01-26 更新:我在 connect.microsoft.com 报告了一个错误

• 2015-01-30 更新:我添加了 CoreInfo 转储作为附加引用。

• 2015-01-30 更新:prime95 也会出现此问题在哪里只提供选择28个线程(与c#无关)

• 2015-01-30 更新:我的工具现在显示处理器等更多信息每个节点的掩码。听起来我无权访问其他节点(我不跑的节点)

• 更新 2015-02-02，我们没有在此特定设备上安装 Citrix服务器(对不起，我错了)

• 更新 2015-02-02，我们联系了 HP...

• 更新2015-02-03，添加更多信息到我的程序中显示每个线程的处理器组和更多的小工具。

• 更新 2015-02-17，在与 HP 开发团队交谈后，我更新了我的答案反射(reflect)我学到的东西。 (只想提一下，我得到了惠普的出色支持)

• 更新 2015-05-13，惠普在“客户咨询”中确认了该问题笔记。请参阅此链接文档 ID:c04650594

我将我的 .Net 4.5(或 4.5.1)App.Config 设置为:

<?xml version="1.0" encoding="utf-8"?>
<configuration>
    <runtime>
        <Thread_UseAllCpuGroups enabled="true"></Thread_UseAllCpuGroups>
        <GCCpuGroup enabled="true"></GCCpuGroup>
        <gcServer enabled="true"></gcServer>
    </runtime>
    <startup> 
        <supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.5.1"/>
    </startup>
</configuration>

这是 CoreInfo 的转储来自微软:

Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz
Intel64 Family 6 Model 63 Stepping 2, GenuineIntel
Microcode signature: 00000023
HTT         *   Hyperthreading enabled
HYPERVISOR  -   Hypervisor is present
VMX         *   Supports Intel hardware-assisted virtualization
SVM         -   Supports AMD hardware-assisted virtualization
X64         *   Supports 64-bit mode

SMX         *   Supports Intel trusted execution
SKINIT      -   Supports AMD SKINIT

NX          *   Supports no-execute page protection
SMEP        *   Supports Supervisor Mode Execution Prevention
SMAP        -   Supports Supervisor Mode Access Prevention
PAGE1GB     *   Supports 1 GB large pages
PAE         *   Supports > 32-bit physical addresses
PAT         *   Supports Page Attribute Table
PSE         *   Supports 4 MB pages
PSE36       *   Supports > 32-bit address 4 MB pages
PGE         *   Supports global bit in page tables
SS          *   Supports bus snooping for cache operations
VME         *   Supports Virtual-8086 mode
RDWRFSGSBASE    *   Supports direct GS/FS base access

FPU         *   Implements i387 floating point instructions
MMX         *   Supports MMX instruction set
MMXEXT      -   Implements AMD MMX extensions
3DNOW       -   Supports 3DNow! instructions
3DNOWEXT    -   Supports 3DNow! extension instructions
SSE         *   Supports Streaming SIMD Extensions
SSE2        *   Supports Streaming SIMD Extensions 2
SSE3        *   Supports Streaming SIMD Extensions 3
SSSE3       *   Supports Supplemental SIMD Extensions 3
SSE4a       -   Supports Streaming SIMDR Extensions 4a
SSE4.1      *   Supports Streaming SIMD Extensions 4.1
SSE4.2      *   Supports Streaming SIMD Extensions 4.2

AES         *   Supports AES extensions
AVX         *   Supports AVX intruction extensions
FMA         *   Supports FMA extensions using YMM state
MSR         *   Implements RDMSR/WRMSR instructions
MTRR        *   Supports Memory Type Range Registers
XSAVE       *   Supports XSAVE/XRSTOR instructions
OSXSAVE     *   Supports XSETBV/XGETBV instructions
RDRAND      *   Supports RDRAND instruction
RDSEED      -   Supports RDSEED instruction

CMOV        *   Supports CMOVcc instruction
CLFSH       *   Supports CLFLUSH instruction
CX8         *   Supports compare and exchange 8-byte instructions
CX16        *   Supports CMPXCHG16B instruction
BMI1        *   Supports bit manipulation extensions 1
BMI2        *   Supports bit manipulation extensions 2
ADX         -   Supports ADCX/ADOX instructions
DCA         *   Supports prefetch from memory-mapped device
F16C        *   Supports half-precision instruction
FXSR        *   Supports FXSAVE/FXSTOR instructions
FFXSR       -   Supports optimized FXSAVE/FSRSTOR instruction
MONITOR     *   Supports MONITOR and MWAIT instructions
MOVBE       *   Supports MOVBE instruction
ERMSB       *   Supports Enhanced REP MOVSB/STOSB
PCLMULDQ    *   Supports PCLMULDQ instruction
POPCNT      *   Supports POPCNT instruction
LZCNT       *   Supports LZCNT instruction
SEP         *   Supports fast system call instructions
LAHF-SAHF   *   Supports LAHF/SAHF instructions in 64-bit mode
HLE         -   Supports Hardware Lock Elision instructions
RTM         -   Supports Restricted Transactional Memory instructions

DE          *   Supports I/O breakpoints including CR4.DE
DTES64      *   Can write history of 64-bit branch addresses
DS          *   Implements memory-resident debug buffer
DS-CPL      *   Supports Debug Store feature with CPL
PCID        *   Supports PCIDs and settable CR4.PCIDE
INVPCID     *   Supports INVPCID instruction
PDCM        *   Supports Performance Capabilities MSR
RDTSCP      *   Supports RDTSCP instruction
TSC         *   Supports RDTSC instruction
TSC-DEADLINE    *   Local APIC supports one-shot deadline timer
TSC-INVARIANT   *   TSC runs at constant rate
xTPR        *   Supports disabling task priority messages

EIST        *   Supports Enhanced Intel Speedstep
ACPI        *   Implements MSR for power management
TM          *   Implements thermal monitor circuitry
TM2         *   Implements Thermal Monitor 2 control
APIC        *   Implements software-accessible local APIC
x2APIC      *   Supports x2APIC

CNXT-ID     -   L1 data cache mode adaptive or BIOS

MCE         *   Supports Machine Check, INT18 and CR4.MCE
MCA         *   Implements Machine Check Architecture
PBE         *   Supports use of FERR#/PBE# pin

PSN         -   Implements 96-bit processor serial number

PREFETCHW   *   Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000F (Basic), 80000008 (Extended).

Logical to Physical Processor Map:
Physical Processor 0 (Hyperthreaded):
**------------------------------------------------------
Physical Processor 1 (Hyperthreaded):
--**----------------------------------------------------
Physical Processor 2 (Hyperthreaded):
----**--------------------------------------------------
Physical Processor 3 (Hyperthreaded):
------**------------------------------------------------
Physical Processor 4 (Hyperthreaded):
--------**----------------------------------------------
Physical Processor 5 (Hyperthreaded):
----------**--------------------------------------------
Physical Processor 6 (Hyperthreaded):
------------**------------------------------------------
Physical Processor 7 (Hyperthreaded):
--------------**----------------------------------------
Physical Processor 8 (Hyperthreaded):
----------------**--------------------------------------
Physical Processor 9 (Hyperthreaded):
------------------**------------------------------------
Physical Processor 10 (Hyperthreaded):
--------------------**----------------------------------
Physical Processor 11 (Hyperthreaded):
----------------------**--------------------------------
Physical Processor 12 (Hyperthreaded):
------------------------**------------------------------
Physical Processor 13 (Hyperthreaded):
--------------------------**----------------------------
Physical Processor 14 (Hyperthreaded):
----------------------------**--------------------------
Physical Processor 15 (Hyperthreaded):
------------------------------**------------------------
Physical Processor 16 (Hyperthreaded):
--------------------------------**----------------------
Physical Processor 17 (Hyperthreaded):
----------------------------------**--------------------
Physical Processor 18 (Hyperthreaded):
------------------------------------**------------------
Physical Processor 19 (Hyperthreaded):
--------------------------------------**----------------
Physical Processor 20 (Hyperthreaded):
----------------------------------------**--------------
Physical Processor 21 (Hyperthreaded):
------------------------------------------**------------
Physical Processor 22 (Hyperthreaded):
--------------------------------------------**----------
Physical Processor 23 (Hyperthreaded):
----------------------------------------------**--------
Physical Processor 24 (Hyperthreaded):
------------------------------------------------**------
Physical Processor 25 (Hyperthreaded):
--------------------------------------------------**----
Physical Processor 26 (Hyperthreaded):
----------------------------------------------------**--
Physical Processor 27 (Hyperthreaded):
------------------------------------------------------**

Logical Processor to Socket Map:
Socket 0:
****************************----------------------------
Socket 1:
----------------------------****************************

Logical Processor to NUMA Node Map:
NUMA Node 0:
****************************----------------------------
NUMA Node 1:
----------------------------****************************
Calculating Cross-NUMA Node Access Cost...

Approximate Cross-NUMA Node Access Cost (relative to fastest):
     00  01
00: 1.0 1.1
01: 1.1 1.1

Logical Processor to Cache Map:
Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**------------------------------------------------------
Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
**------------------------------------------------------
Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
**------------------------------------------------------
Unified Cache       1, Level 3,   35 MB, Assoc  20, LineSize  64
****************************----------------------------
Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**----------------------------------------------------
Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
--**----------------------------------------------------
Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64
--**----------------------------------------------------
Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**--------------------------------------------------
Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
----**--------------------------------------------------
Unified Cache       3, Level 2,  256 KB, Assoc   8, LineSize  64
----**--------------------------------------------------
Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**------------------------------------------------
Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
------**------------------------------------------------
Unified Cache       4, Level 2,  256 KB, Assoc   8, LineSize  64
------**------------------------------------------------
Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**----------------------------------------------
Instruction Cache   4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**----------------------------------------------
Unified Cache       5, Level 2,  256 KB, Assoc   8, LineSize  64
--------**----------------------------------------------
Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**--------------------------------------------
Instruction Cache   5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**--------------------------------------------
Unified Cache       6, Level 2,  256 KB, Assoc   8, LineSize  64
----------**--------------------------------------------
Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**------------------------------------------
Instruction Cache   6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**------------------------------------------
Unified Cache       7, Level 2,  256 KB, Assoc   8, LineSize  64
------------**------------------------------------------
Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**----------------------------------------
Instruction Cache   7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**----------------------------------------
Unified Cache       8, Level 2,  256 KB, Assoc   8, LineSize  64
--------------**----------------------------------------
Data Cache          8, Level 1,   32 KB, Assoc   8, LineSize  64
----------------**--------------------------------------
Instruction Cache   8, Level 1,   32 KB, Assoc   8, LineSize  64
----------------**--------------------------------------
Unified Cache       9, Level 2,  256 KB, Assoc   8, LineSize  64
----------------**--------------------------------------
Data Cache          9, Level 1,   32 KB, Assoc   8, LineSize  64
------------------**------------------------------------
Instruction Cache   9, Level 1,   32 KB, Assoc   8, LineSize  64
------------------**------------------------------------
Unified Cache      10, Level 2,  256 KB, Assoc   8, LineSize  64
------------------**------------------------------------
Data Cache         10, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------**----------------------------------
Instruction Cache  10, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------**----------------------------------
Unified Cache      11, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------**----------------------------------
Data Cache         11, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------**--------------------------------
Instruction Cache  11, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------**--------------------------------
Unified Cache      12, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------**--------------------------------
Data Cache         12, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------**------------------------------
Instruction Cache  12, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------**------------------------------
Unified Cache      13, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------**------------------------------
Data Cache         13, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------**----------------------------
Instruction Cache  13, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------**----------------------------
Unified Cache      14, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------**----------------------------
Data Cache         14, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------**--------------------------
Instruction Cache  14, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------**--------------------------
Unified Cache      15, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------**--------------------------
Unified Cache      16, Level 3,   35 MB, Assoc  20, LineSize  64
----------------------------****************************
Data Cache         15, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------**------------------------
Instruction Cache  15, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------**------------------------
Unified Cache      17, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------**------------------------
Data Cache         16, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------**----------------------
Instruction Cache  16, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------**----------------------
Unified Cache      18, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------**----------------------
Data Cache         17, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------**--------------------
Instruction Cache  17, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------**--------------------
Unified Cache      19, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------**--------------------
Data Cache         18, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------**------------------
Instruction Cache  18, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------**------------------
Unified Cache      20, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------**------------------
Data Cache         19, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------**----------------
Instruction Cache  19, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------**----------------
Unified Cache      21, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------------**----------------
Data Cache         20, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------**--------------
Instruction Cache  20, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------**--------------
Unified Cache      22, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------**--------------
Data Cache         21, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------**------------
Instruction Cache  21, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------**------------
Unified Cache      23, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------------**------------
Data Cache         22, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------**----------
Instruction Cache  22, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------**----------
Unified Cache      24, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------------------**----------
Data Cache         23, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------**--------
Instruction Cache  23, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------**--------
Unified Cache      25, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------**--------
Data Cache         24, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------**------
Instruction Cache  24, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------**------
Unified Cache      26, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------------------**------
Data Cache         25, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------------**----
Instruction Cache  25, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------------------------------**----
Unified Cache      27, Level 2,  256 KB, Assoc   8, LineSize  64
--------------------------------------------------**----
Data Cache         26, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------**--
Instruction Cache  26, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------------------------------**--
Unified Cache      28, Level 2,  256 KB, Assoc   8, LineSize  64
----------------------------------------------------**--
Data Cache         27, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------------**
Instruction Cache  27, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------------------------------**
Unified Cache      29, Level 2,  256 KB, Assoc   8, LineSize  64
------------------------------------------------------**

Logical Processor to Group Map:
Group 0:
****************************----------------------------
Group 1:
----------------------------****************************

这是 MsInfo32 命令转储(有关服务器的信息):

OS Name            Microsoft Windows Server 2012 R2 Standard
Version               6.3.9600 Build 9600
Other OS Description    Not Available
OS Manufacturer            Microsoft Corporation
System Name   EMTP6
System Manufacturer   HP
System Model  ProLiant DL360 Gen9
System Type     x64-based PC
System SKU       755258-B21
Processor           Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
Processor           Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
BIOS Version/Date         HP P89, 7/11/2014
SMBIOS Version              2.8
Embedded Controller Version 2.02
BIOS Mode         UEFI
Platform Role   Enterprise Server
Secure Boot State           Off
PCR7 Configuration       Not Available
Windows Directory        ---removed
System Directory            ---removed
Boot Device       \Device\HarddiskVolume2
Locale   United States
Hardware Abstraction Layer      Version = "6.3.9600.17196"
User Name         Not Available
Time Zone          Eastern Standard Time
Installed Physical Memory (RAM)          256 GB
Total Physical Memory 256 GB
Available Physical Memory       246 GB
Total Virtual Memory   294 GB
Available Virtual Memory          283 GB
Page File Space               38.0 GB
Page File             ---removed
Hyper-V - VM Monitor Mode Extensions            Yes
Hyper-V - Second Level Address Translation Extensions             Yes
Hyper-V - Virtualization Enabled in Firmware  Yes
Hyper-V - Data Execution Protection    Yes

这是 TaskManager 的屏幕截图和我的程序结果:

或者，如果 Windows 决定在节点 1 上启动它:

来自另一台服务器的预期行为:

OS Name Microsoft Windows Server 2008 HPC Edition
Version 6.1.7601 Service Pack 1 Build 7601
Other OS Description    Not Available
OS Manufacturer Microsoft Corporation
System Name COMPUTE-13-6
System Manufacturer HP
System Model    ProLiant DL160 G6
System Type x64-based PC
Processor   Intel(R) Xeon(R) CPU           X5675  @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
Processor   Intel(R) Xeon(R) CPU           X5675  @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
BIOS Version/Date   HP O33, 7/1/2013
SMBIOS Version  2.7
Windows Directory   C:\Windows
System Directory    C:\Windows\system32
Boot Device \Device\HarddiskVolume1
Locale  United States
Hardware Abstraction Layer  Version = "6.1.7601.17514"
User Name   Not Available
Time Zone   Eastern Standard Time
Installed Physical Memory (RAM) 48.0 GB
Total Physical Memory   48.0 GB
Available Physical Memory   40.9 GB
Total Virtual Memory    96.0 GB
Available Virtual Memory    88.4 GB
Page File Space 48.0 GB
Page File   C:\pagefile.sys

注意:我认为我们通过更改 bios 中的“Interleaved Memory”参数解决了这个问题。但我给了我们奇怪的结果。根据Microsoft Technet我们将 BIOS 设置恢复为“NON-Interleaved memory”**(操作系统需要将系统视为 NUMA)。

Answer 1

该错误已由新的(尚未发布的)HP Bios 修复(在撰写本文时)。

新的 Bios(针对 HP Proliant DL360 和 DL380 Gen9)引入了一个新设置:“NUMA Group Size Optimization”，可以选择 [Clustered - default] 或 [Flat]。惠普表示将其设置为平坦。

由于服务器可用性，此答案的截图部分是在 DL380 而不是 DL360 上进行的。但我希望在 DL360 上有同样的行为。问题消失了，我们只有一组。

据我所知，操作系统与 BIOS 通信以了解 CPU 配置。 Bios 在操作系统如何向应用程序(处理器组、亲和性等)呈现可用的逻辑处理器方面发挥着重要作用。

关于 Microsoft 文档 Supporting Systems That Have More Than 64 Processors和 Processor Groups明确指出，只有当逻辑处理器 (LC) 计数 >64 时，才会创建多个处理器组。在我们的服务器 (56 LC) 上，Numa Architecture 设置为“Clustered”，我们有 2 个处理器组。在 HP Bios 开发团队工作的一位硬件工程师向我解释说，当设置为“集群”时，Bios 通过将逻辑处理器的实际数量填充到 72 个逻辑处理器(E5 v3 Family 的最大逻辑处理器数量)来欺骗 Windows。在我们的DL360中，LC的真实数量是56个。这就是为什么我们添加 2 个组而不是 1 个组的原因。Microsoft 文档似乎是准确的。我个人认为最好尽可能为每个 numa 节点创建 1 个组，但在我们的例子中，存在一个错误。当 HP Bios 设置设置为 Clustered(默认)时，很难在 HP 或 Microsoft 之间知道有什么问题，但 Microsoft 似乎不支持该选项，这似乎会导致我们的问题。

在适用于 DL360 和 DL380 的 HP Bios 上，Bios 配置“Numa Configuration”设置为“Clustered”(默认)将创建 2 个组，尽管只有 56 个逻辑处理器(超线程时)。结果是任何应用程序一次只能看到一个处理器。也可能是由于惠普通过填充虚假数量的逻辑处理器来欺骗 Windows。听起来微软并不希望如此。我们的 C# 应用程序无法在 2 个组上运行。很难将惠普做出他们无法预料的事情的行为归咎于微软。也许有一天，当 LC <= 64 时，Windows 会支持许多组。

关于 Prime95。这款CPU压力测试软件不错documentation on Wikipedia明确指出它将仅加载到一个处理器组(在“限制”部分)。