c - 操作系统导致的 irq 延迟是多少？

Question

• 如何估计 ARM 处理器上的 irq 延迟？
• irq 延迟的定义是什么？

Answer 1

1. 中断请求 (irq) 延迟是中断请求从中断源传输到服务点所需的时间。

2. 因为有不同的中断来自不同的来源，通过不同的路径，显然它们的延迟取决于中断的类型。您可以找到对特定中断的延迟(值和原因)进行很好解释的表格 on ARM site

您可以在 ARM9E-S Core Technical Reference Manual 中找到更多相关信息:

4.3 Maximum interrupt latency

If the sampled signal is asserted at the same time as a multicycle instruction has started its second or later cycle of execution, the interrupt exception entry does not start until the instruction has completed.

The longest LDM instruction is one that loads all of the registers, including the PC.

Counting the first Execute cycle as 1, the LDM takes 16 cycles.

• The last word to be transferred by the LDM is transferred in cycle 17, and the abort status for the transfer is returned in this cycle.

• If a Data Abort happens, the processor detects this in cycle 18 and prepares for the Data Abort exception entry in cycle 19.

• Cycles 20 and 21 are the Fetch and Decode stages of the Data Abort entry respectively.

• During cycle 22, the processor prepares for FIQ entry, issuing Fetch and Decode cycles in cycles 23 and 24.

• Therefore, the first instruction in the FIQ routine enters the Execute stage of the pipeline in stage 25, giving a worst-case latency of 24 cycles.

和

Minimum interrupt latency

The minimum latency for FIQ or IRQ is the shortest time the request can be sampled by the input register (one cycle), plus the exception entry time (three cycles). The first interrupt instruction enters the Execute pipeline stage four cycles after the interrupt is asserted