I've recently come across this description of a single processor cache saying that it's

我最近看到这样一个单处理器缓存的描述，说它是

"Word addressed (addresses are left shifted by 2 by adding “00” to end of address inside the processor, this implies that it can address 2^32*4 = 16GBytes of memory"

“已寻址的字(地址左移2，在处理器内部的地址末尾加上”00“，这意味着它可以寻址2^32*4=16 GB的内存”

I understand that word addressing means that each consecutive address holds a word of data versus byte addressing which holds a byte of data at each address. I further understand that left shifting address by 2 means multiplying the address by 4 so we are trying to obtain multiples of 4, but doesn't that imply that each address holds a byte of data thus this is not word addressing but in fact byte addressing and the processor has logic in which we only access a word at a time despite what the memory is like?

据我所知，字寻址意味着每个连续的地址保存一个字的数据，而字节寻址则在每个地址保存一个字节的数据。我进一步理解，左移地址2意味着乘以4的地址，所以我们试图获得4的倍数，但这不意味着每个地址持有一个字节的数据，因此这不是字寻址，但事实上字节寻址和处理器的逻辑，我们只访问一个字的时间，不管内存是什么样的？

So far I am confused on whether word addressed just means we have logic in place to access a word at a time or the actual memory is formatted in a way that each address will hold a whole word and not a byte

到目前为止，我感到困惑的是，字寻址只是意味着我们具有一次访问一个字的逻辑，还是实际存储器的格式化方式是每个地址将保存整个字而不是一个字节

It would help to know where this description came from but nevertheless, perhaps the following helps illuminate what might be going on.

知道这个描述是从哪里来的将会有所帮助，但尽管如此，下面的内容可能有助于阐明可能发生的事情。

When we talk about byte- versus word-addressable memories (caches, RAM, SSDs, or otherwise) we are referring to the minimum width of data that can be referenced by an address. Regardless of the addressable width of a single location, the memory will still hold bytes, grouped together in 4s for words, or 8s for double-words, etc. Just the same as a byte is always made of bits (in modern systems: typically 8 bits per byte, but that's not always the case.)

当我们谈论字节可寻址存储器与字可寻址存储器(缓存、RAM、SSD或其他)时，我们指的是地址可以引用的最小数据宽度。无论单个位置的可寻址宽度如何，内存仍将保存字节，对于字，分组为4，对于双字，分组为8，依此类推。就像字节总是由位组成一样(在现代系统中：通常是每字节8位，但情况并不总是如此)。

For the following exmaples, let's assume we have 8 address bits. (Though real systems usually have between 16 and 54 address bits. None, that I know of, have full 64-bit addresses.)

对于下面的示例，让我们假设我们有8个地址位。(尽管实际系统通常具有16到54个地址位。据我所知，没有一个拥有完整的64位地址。)

With a byte-addressable memory, 8 address bits allows us to reference 2^8 locations. To get the size of memory, we multiply by the size (in bytes) of each addressed location. That gives us 2^8 * 1byte = 256 bytes

使用字节可寻址存储器，8个地址位允许我们引用2^8个位置。为了得到内存的大小，我们乘以每个寻址位置的大小(以字节为单位)。这给了我们2^8*1byte=256个字节

With a word-addressable memory, 8 address bits allows us to reference the same number of locations (2^8.) However, the size (in bytes) of each addressed location is now 4 bytes. That gives us 2^8 * 4 = 1024 bytes (1KiB.)

对于字可寻址存储器，8个地址位允许我们引用相同数量的位置(2^8)。但是，每个寻址位置的大小(以字节为单位)现在是4个字节。这给我们提供了2^8*4=1024字节(1KiB。)

Now, the confusion starts to arise when we look at where the address bits are coming from.

现在，当我们查看地址位从哪里来时，混淆开始出现。

Let's say I have 2 instruction sets (ISAs). Both have load/store instructions that take an address to memory. In one ISA, the instructions use byte-addressing. In the other, the instructions use word-addressing.

假设我有两个指令集(ISA)。两者都有将地址带到内存的加载/存储指令。在一个ISA中，指令使用字节寻址。在另一种情况下，指令使用字寻址。

ld r1, 0x12

Looking at the byte index in memory that such a load instruction accesses, what would we expect in the two ISAs?

看看这样的加载指令访问的内存中的字节索引，我们会在两个ISA中期待什么？

In the byte-addressed ISA, it's easy: the byte address is 0x12 (decimal: 18.)

在字节寻址的ISA中，这很容易：字节地址是0x12(十进制：18)。

In the word-addressed ISA, it's different. The 0x12 is an address that refers to a word in memory, rather than an individual byte. To get the index in memory as a number of bytes, we multiply by 4 (bytes per word.) That is to say, we shift the address left by 2. So 0x12 becomes 0x48 (decimal: 72.)

在以单词为地址的ISA中，情况就不同了。0x12是指存储器中的字而不是单个字节的地址。要以字节数表示内存中的索引，我们需要乘以4(每个字的字节数)。也就是说，我们将地址左移2。因此0x12变成0x48(十进制：72。)

Okay, so an Instruction Set Architecture (ISA) can define how a number is interpreted - whether it's a word-address or byte-address.

好的，指令集体系结构(ISA)可以定义如何解释一个数字--它是字地址还是字节地址。

Additionally, when it comes to caches, hardware doesn't behave in the neat way the ISA presents to software engineers.

此外，当涉及到缓存时，硬件的行为并不像ISA向软件工程师展示的那样简洁。

For example, modern caches may present a dword-addressed, word-addressed or byte-addressed interface to the processor core (or other variations.) In a word-addressed scenario, to store an individual byte, the cache controller must first load the whole word in which the byte resides into a temporary internal buffer, update it with the byte being stored, then store that word back into the cache's SRAM array. This is known as a read-modify-write (RMW.)

例如，现代高速缓存可以向处理器核心(或其他变体)提供双字寻址、字寻址或字节寻址的接口。在字寻址方案中，要存储单个字节，高速缓存控制器必须首先将该字节所在的整个字加载到临时内部缓冲区中，用存储的字节更新它，然后将该字存储回高速缓存的SRAM数组中。这称为读-修改-写(RMW)。

See Are there any modern CPUs where a cached byte store is actually slower than a word store? for some real examples such as ARM Cortex-A15 where ARM's manual explains that updating the ECC (Error Correction Code) data for the 32-bit chunk is part of the reason for an RMW being needed for isolated byte or 16-bit stores. (ARM is a byte-addressable ISA, unlike the one described in the question.)

请参阅是否有任何现代CPU的缓存字节存储实际上比字存储慢？对于一些真实的例子，例如ARM Cortex-A15，ARM的手册解释说，更新32位块的ECC（纠错码）数据是隔离字节或16位存储需要RMW的部分原因。(ARM是字节可寻址ISA，与问题中描述的ISA不同。）

RMW is relatively straightforward for a single byte. It's more complex for, say, a half-word (i.e. 2 byte) load/store on a byte-addressable memory. This is because the 2 bytes may cross a natural word boundary. Thus, it may be that two whole words must be loaded/stored to access a single half-word.

对于单字节而言，RMW相对简单。比方说，在字节可寻址存储器上进行半字(即2字节)加载/存储要复杂得多。这是因为这2个字节可能跨越自然字边界。因此，可能必须加载/存储两个完整字才能访问单个半字。

With word-addressable memory, the half-word will (only ever) be the bottom 2 bytes of a naturally aligned word, making such a 2-word RMW impossible/unnecessary. However, it would also be impossible to directly perform a half-word load/store on the upper half-word of any given word, since word-addressing doesn't allow for referencing that upper half-word directly. (Some ISAs offer separate load/store instructions to access the different positions within a word - such as load half-word/load-byte instructions that take a word address and an index within the word.)

对于字可寻址存储器，半字将(永远)是自然对齐字的底部2个字节，使得这样的2字RMW不可能/不必要。然而，也不可能在任何给定字的上半字上直接执行半字加载/存储，因为字寻址不允许直接引用该上半字。(有些ISA提供单独的加载/存储指令来访问字内的不同位置，例如加载半字/加载字节指令，这些指令接受字地址和字内的索引。)

Going back to the cache: On the other side of the cache (the interface to main memory or other layers of cache), neither byte- nor word-addressing are used. Instead, row-addresses are used, where a row may be 64, 128 or more bytes in size.

返回到缓存：在缓存的另一端(到主内存或其他缓存层的接口)，既不使用字节寻址，也不使用字寻址。取而代之的是使用行地址，其中行的大小可以是64、128或更多字节。

So, what's the point of all this? At the end of the day, it all comes down the physical hardware resources. If you know that something is word-addressed, you don't need to store the bottom 2 bits of the address because (if they were needed at all) they are guaranteed to always be zero. We can save silicon by not storing/communicating more bits than necessary. We can also simplify hardware logic by knowing certain scenarios are impossible (such as the split half-word load/store described earlier.) Knowing they're impossible cases means we don't need logic (i.e. hardware) to handle them.

那么，这一切有什么意义呢？归根结底，这一切都会影响到物理硬件资源。如果您知道某些内容是按字寻址的，则不需要存储地址的最低2位，因为(如果需要的话)它们保证始终为零。我们可以通过不存储/传递不必要的更多位来节省硅。我们还可以通过知道某些场景是不可能的(例如前面描述的拆分半字加载/存储)来简化硬件逻辑。知道它们是不可能的情况意味着我们不需要逻辑(即硬件)来处理它们。

Additionally, if you consider the bits needed to encode an instruction (in either of the earlier 2 ISA examples), by using word-addressing, the ISA can access (/address) more memory without needing more encoding bits per instruction.

此外，如果考虑编码指令所需的位(在前面的两个ISA示例中)，通过使用字寻址，ISA可以访问(/地址)更多内存，而不需要每条指令更多的编码位。

Word-addressing also offers other practical benefits. Ask yourself, why don't we have "bit addressing"? Most memory cannot be accessed on a bit-by-bit or byte-by-byte basis. At best, a whole word or whole row must be loaded/stored. So word-addressing saves hardware the effort of masking off the bottom two address bits, loading a word, then masking&shifting the loaded word to make it align to the address.

单词寻址还提供了其他实际好处。问问你自己，为什么我们没有“位寻址”？大多数内存不能逐位或逐字节地访问。最多只能加载/存储整个单词或整行。因此，字寻址省去了硬件屏蔽底部两个地址位的工作，加载一个字，然后屏蔽和移位加载的字，使其与地址对齐。

For loads/stores, the issue of word- versus byte-addressing also overlaps with the issue of (natural) alignment of the address. But that's a topic for another question.

对于加载/存储，字对字节寻址的问题也与地址(自然)对齐的问题重叠。但这是另一个问题的主题。